JPS644666B2 - - Google Patents

Info

Publication number
JPS644666B2
JPS644666B2 JP57501423A JP50142382A JPS644666B2 JP S644666 B2 JPS644666 B2 JP S644666B2 JP 57501423 A JP57501423 A JP 57501423A JP 50142382 A JP50142382 A JP 50142382A JP S644666 B2 JPS644666 B2 JP S644666B2
Authority
JP
Japan
Prior art keywords
region
oxide
type
layer
mask pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57501423A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58500504A (ja
Inventor
Richaado Eichi Rein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPS58500504A publication Critical patent/JPS58500504A/ja
Publication of JPS644666B2 publication Critical patent/JPS644666B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H10P76/40—
    • H10W10/0125—
    • H10W10/13—
    • H10W15/00—
    • H10W15/01—
    • H10W46/00—
    • H10W46/501—

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP57501423A 1981-04-06 1982-03-22 自己整合埋込みチャネルを具えた半導体装置の製造方法 Granted JPS58500504A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/251,615 US4381956A (en) 1981-04-06 1981-04-06 Self-aligned buried channel fabrication process
US251615 1988-09-29

Publications (2)

Publication Number Publication Date
JPS58500504A JPS58500504A (ja) 1983-03-31
JPS644666B2 true JPS644666B2 (enExample) 1989-01-26

Family

ID=22952710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57501423A Granted JPS58500504A (ja) 1981-04-06 1982-03-22 自己整合埋込みチャネルを具えた半導体装置の製造方法

Country Status (5)

Country Link
US (1) US4381956A (enExample)
EP (1) EP0075588B1 (enExample)
JP (1) JPS58500504A (enExample)
DE (1) DE3274924D1 (enExample)
WO (1) WO1982003495A1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4450021A (en) * 1982-02-22 1984-05-22 American Microsystems, Incorporated Mask diffusion process for forming Zener diode or complementary field effect transistors
US4546375A (en) * 1982-06-24 1985-10-08 Rca Corporation Vertical IGFET with internal gate and method for making same
FR2548453B1 (fr) * 1983-06-30 1986-11-14 Thomson Csf Procede de fabrication d'un transistor a effet de champ a jonction vertical haute frequence
IT1213192B (it) * 1984-07-19 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione di transistori ad effetto di campo agate isolato (igfet) ad elevata velocita' di risposta in circuiti integrati ad alta densita'.
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
US4642259A (en) * 1985-04-26 1987-02-10 Triquint Semiconductors, Inc. Source-side self-aligned gate process
US4717687A (en) * 1986-06-26 1988-01-05 Motorola Inc. Method for providing buried layer delineation
JPS63185061A (ja) * 1987-01-28 1988-07-30 Toshiba Corp 半導体装置の製造方法
JPS6410644A (en) * 1987-07-02 1989-01-13 Mitsubishi Electric Corp Manufacture of semiconductor device
US4784964A (en) * 1987-10-19 1988-11-15 Motorola Inc. EPI defect reduction using rapid thermal annealing
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
US4876214A (en) * 1988-06-02 1989-10-24 Tektronix, Inc. Method for fabricating an isolation region in a semiconductor substrate
US4853344A (en) * 1988-08-12 1989-08-01 Advanced Micro Devices, Inc. Method of integrated circuit isolation oxidizing walls of isolation slot, growing expitaxial layer over isolation slot, and oxidizing epitaxial layer over isolation slot
US5132765A (en) * 1989-09-11 1992-07-21 Blouse Jeffrey L Narrow base transistor and method of fabricating same
US5008207A (en) * 1989-09-11 1991-04-16 International Business Machines Corporation Method of fabricating a narrow base transistor
US5942805A (en) * 1996-12-20 1999-08-24 Intel Corporation Fiducial for aligning an integrated circuit die
US9577134B2 (en) 2013-12-09 2017-02-21 Sunpower Corporation Solar cell emitter region fabrication using self-aligned implant and cap
US9401450B2 (en) 2013-12-09 2016-07-26 Sunpower Corporation Solar cell emitter region fabrication using ion implantation
US9263625B2 (en) 2014-06-30 2016-02-16 Sunpower Corporation Solar cell emitter region fabrication using ion implantation
US20160284913A1 (en) 2015-03-27 2016-09-29 Staffan WESTERBERG Solar cell emitter region fabrication using substrate-level ion implantation

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL169121C (nl) * 1970-07-10 1982-06-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon.
US3947299A (en) * 1971-05-22 1976-03-30 U.S. Philips Corporation Method of manufacturing semiconductor devices
JPS5228550B2 (enExample) * 1972-10-04 1977-07-27
US4002511A (en) * 1975-04-16 1977-01-11 Ibm Corporation Method for forming masks comprising silicon nitride and novel mask structures produced thereby
FR2341201A1 (fr) * 1976-02-16 1977-09-09 Radiotechnique Compelec Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu
US4062699A (en) * 1976-02-20 1977-12-13 Western Digital Corporation Method for fabricating diffusion self-aligned short channel MOS device
US4184172A (en) * 1976-12-06 1980-01-15 Massachusetts Institute Of Technology Dielectric isolation using shallow oxide and polycrystalline silicon
US4149915A (en) * 1978-01-27 1979-04-17 International Business Machines Corporation Process for producing defect-free semiconductor devices having overlapping high conductivity impurity regions
US4144101A (en) * 1978-06-05 1979-03-13 International Business Machines Corporation Process for providing self-aligned doping regions by ion-implantation and lift-off
US4151010A (en) * 1978-06-30 1979-04-24 International Business Machines Corporation Forming adjacent impurity regions in a semiconductor by oxide masking
US4182636A (en) * 1978-06-30 1980-01-08 International Business Machines Corporation Method of fabricating self-aligned contact vias
US4261763A (en) * 1979-10-01 1981-04-14 Burroughs Corporation Fabrication of integrated circuits employing only ion implantation for all dopant layers

Also Published As

Publication number Publication date
EP0075588A1 (en) 1983-04-06
US4381956A (en) 1983-05-03
DE3274924D1 (en) 1987-02-05
EP0075588A4 (en) 1984-07-18
WO1982003495A1 (en) 1982-10-14
JPS58500504A (ja) 1983-03-31
EP0075588B1 (en) 1986-12-30

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