DE3274924D1 - Process for fabricating a self-aligned buried channel and the product thereof - Google Patents
Process for fabricating a self-aligned buried channel and the product thereofInfo
- Publication number
- DE3274924D1 DE3274924D1 DE8282901267T DE3274924T DE3274924D1 DE 3274924 D1 DE3274924 D1 DE 3274924D1 DE 8282901267 T DE8282901267 T DE 8282901267T DE 3274924 T DE3274924 T DE 3274924T DE 3274924 D1 DE3274924 D1 DE 3274924D1
- Authority
- DE
- Germany
- Prior art keywords
- fabricating
- self
- product
- buried channel
- aligned buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/251,615 US4381956A (en) | 1981-04-06 | 1981-04-06 | Self-aligned buried channel fabrication process |
PCT/US1982/000355 WO1982003495A1 (en) | 1981-04-06 | 1982-03-22 | Process for fabricating a self-aligned buried channel and the product thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3274924D1 true DE3274924D1 (en) | 1987-02-05 |
Family
ID=22952710
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282901267T Expired DE3274924D1 (en) | 1981-04-06 | 1982-03-22 | Process for fabricating a self-aligned buried channel and the product thereof |
Country Status (5)
Country | Link |
---|---|
US (1) | US4381956A (de) |
EP (1) | EP0075588B1 (de) |
JP (1) | JPS58500504A (de) |
DE (1) | DE3274924D1 (de) |
WO (1) | WO1982003495A1 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4450021A (en) * | 1982-02-22 | 1984-05-22 | American Microsystems, Incorporated | Mask diffusion process for forming Zener diode or complementary field effect transistors |
US4546375A (en) * | 1982-06-24 | 1985-10-08 | Rca Corporation | Vertical IGFET with internal gate and method for making same |
FR2548453B1 (fr) * | 1983-06-30 | 1986-11-14 | Thomson Csf | Procede de fabrication d'un transistor a effet de champ a jonction vertical haute frequence |
IT1213192B (it) * | 1984-07-19 | 1989-12-14 | Ates Componenti Elettron | Processo per la fabbricazione di transistori ad effetto di campo agate isolato (igfet) ad elevata velocita' di risposta in circuiti integrati ad alta densita'. |
US4574469A (en) * | 1984-09-14 | 1986-03-11 | Motorola, Inc. | Process for self-aligned buried layer, channel-stop, and isolation |
US4583282A (en) * | 1984-09-14 | 1986-04-22 | Motorola, Inc. | Process for self-aligned buried layer, field guard, and isolation |
US4642259A (en) * | 1985-04-26 | 1987-02-10 | Triquint Semiconductors, Inc. | Source-side self-aligned gate process |
US4717687A (en) * | 1986-06-26 | 1988-01-05 | Motorola Inc. | Method for providing buried layer delineation |
JPS63185061A (ja) * | 1987-01-28 | 1988-07-30 | Toshiba Corp | 半導体装置の製造方法 |
JPS6410644A (en) * | 1987-07-02 | 1989-01-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US4784964A (en) * | 1987-10-19 | 1988-11-15 | Motorola Inc. | EPI defect reduction using rapid thermal annealing |
US4925806A (en) * | 1988-03-17 | 1990-05-15 | Northern Telecom Limited | Method for making a doped well in a semiconductor substrate |
US4876214A (en) * | 1988-06-02 | 1989-10-24 | Tektronix, Inc. | Method for fabricating an isolation region in a semiconductor substrate |
US4853344A (en) * | 1988-08-12 | 1989-08-01 | Advanced Micro Devices, Inc. | Method of integrated circuit isolation oxidizing walls of isolation slot, growing expitaxial layer over isolation slot, and oxidizing epitaxial layer over isolation slot |
US5008207A (en) * | 1989-09-11 | 1991-04-16 | International Business Machines Corporation | Method of fabricating a narrow base transistor |
US5132765A (en) * | 1989-09-11 | 1992-07-21 | Blouse Jeffrey L | Narrow base transistor and method of fabricating same |
US5942805A (en) * | 1996-12-20 | 1999-08-24 | Intel Corporation | Fiducial for aligning an integrated circuit die |
US9401450B2 (en) | 2013-12-09 | 2016-07-26 | Sunpower Corporation | Solar cell emitter region fabrication using ion implantation |
US9577134B2 (en) | 2013-12-09 | 2017-02-21 | Sunpower Corporation | Solar cell emitter region fabrication using self-aligned implant and cap |
US9263625B2 (en) | 2014-06-30 | 2016-02-16 | Sunpower Corporation | Solar cell emitter region fabrication using ion implantation |
US20160284913A1 (en) | 2015-03-27 | 2016-09-29 | Staffan WESTERBERG | Solar cell emitter region fabrication using substrate-level ion implantation |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL169121C (nl) * | 1970-07-10 | 1982-06-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon. |
US3947299A (en) * | 1971-05-22 | 1976-03-30 | U.S. Philips Corporation | Method of manufacturing semiconductor devices |
JPS5228550B2 (de) * | 1972-10-04 | 1977-07-27 | ||
US4002511A (en) * | 1975-04-16 | 1977-01-11 | Ibm Corporation | Method for forming masks comprising silicon nitride and novel mask structures produced thereby |
FR2341201A1 (fr) * | 1976-02-16 | 1977-09-09 | Radiotechnique Compelec | Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu |
US4062699A (en) * | 1976-02-20 | 1977-12-13 | Western Digital Corporation | Method for fabricating diffusion self-aligned short channel MOS device |
US4184172A (en) * | 1976-12-06 | 1980-01-15 | Massachusetts Institute Of Technology | Dielectric isolation using shallow oxide and polycrystalline silicon |
US4149915A (en) * | 1978-01-27 | 1979-04-17 | International Business Machines Corporation | Process for producing defect-free semiconductor devices having overlapping high conductivity impurity regions |
US4144101A (en) * | 1978-06-05 | 1979-03-13 | International Business Machines Corporation | Process for providing self-aligned doping regions by ion-implantation and lift-off |
US4182636A (en) * | 1978-06-30 | 1980-01-08 | International Business Machines Corporation | Method of fabricating self-aligned contact vias |
US4151010A (en) * | 1978-06-30 | 1979-04-24 | International Business Machines Corporation | Forming adjacent impurity regions in a semiconductor by oxide masking |
US4261763A (en) * | 1979-10-01 | 1981-04-14 | Burroughs Corporation | Fabrication of integrated circuits employing only ion implantation for all dopant layers |
-
1981
- 1981-04-06 US US06/251,615 patent/US4381956A/en not_active Expired - Lifetime
-
1982
- 1982-03-22 WO PCT/US1982/000355 patent/WO1982003495A1/en active IP Right Grant
- 1982-03-22 JP JP57501423A patent/JPS58500504A/ja active Granted
- 1982-03-22 EP EP82901267A patent/EP0075588B1/de not_active Expired
- 1982-03-22 DE DE8282901267T patent/DE3274924D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS58500504A (ja) | 1983-03-31 |
WO1982003495A1 (en) | 1982-10-14 |
EP0075588A1 (de) | 1983-04-06 |
EP0075588B1 (de) | 1986-12-30 |
US4381956A (en) | 1983-05-03 |
EP0075588A4 (de) | 1984-07-18 |
JPS644666B2 (de) | 1989-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3274924D1 (en) | Process for fabricating a self-aligned buried channel and the product thereof | |
DE3264835D1 (en) | Shoe-sole, method and mould for making the same | |
DE3278925D1 (en) | Process for the manufacture of a transistor | |
JPS5780029A (en) | Device for manufacturing thermoplastic pipe | |
GB2079048B (en) | A semiconductor device and a process for the production thereof | |
JPS57153087A (en) | Device for producing gaseous product | |
EP0102392A4 (de) | Verfahren und gerät zur herstellung von blattähnlichem formmaterial. | |
EP0199818A4 (de) | Agglomerat und dessen herstellungsverfahren. | |
EP0199497A3 (en) | Process for fabricating a self-aligned bipolar transistor | |
GB2071703B (en) | Contact element and process for producing the same | |
AU8228282A (en) | Thermoplastic insulation | |
DE3165316D1 (en) | 2-substituted-5-trifluoromethylpyridines and a process for producing the same | |
GB2073635B (en) | Segmented female die | |
GB2110963B (en) | Die forming method | |
DE3172926D1 (en) | Continuous vulcanizer | |
DE3165481D1 (en) | A polysilicon-base self-aligned bipolar transistor process | |
GB2149335B (en) | Extrusion die and a method for the manufacture thereof | |
JPS57143346A (en) | Thermoplastic forming material | |
GB8308380D0 (en) | Forming dies | |
DE3276582D1 (en) | Novel endo-deoxyribonuclease and process for the production thereof | |
PT74824A (en) | Process for preparing a systemic pesticide product | |
JPS57142808A (en) | Device for manufacturing bagged product | |
JPS57143344A (en) | Thermoplastic forming material | |
IL62113A0 (en) | Piperidinoquinazolines and a process for the preparation thereof | |
ZA821491B (en) | Novel n-acyl-polypeptides and processes for the production thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |