JPS6446291A - Bit line equalizing circuit - Google Patents

Bit line equalizing circuit

Info

Publication number
JPS6446291A
JPS6446291A JP62202021A JP20202187A JPS6446291A JP S6446291 A JPS6446291 A JP S6446291A JP 62202021 A JP62202021 A JP 62202021A JP 20202187 A JP20202187 A JP 20202187A JP S6446291 A JPS6446291 A JP S6446291A
Authority
JP
Japan
Prior art keywords
bit line
boosting
equalizing circuit
equalizing
line equalizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62202021A
Other languages
English (en)
Other versions
JP2623257B2 (ja
Inventor
Masayoshi Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Original Assignee
Texas Instruments Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd filed Critical Texas Instruments Japan Ltd
Priority to JP62202021A priority Critical patent/JP2623257B2/ja
Publication of JPS6446291A publication Critical patent/JPS6446291A/ja
Application granted granted Critical
Publication of JP2623257B2 publication Critical patent/JP2623257B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Dram (AREA)
JP62202021A 1987-08-13 1987-08-13 ダイナミック型半導体記憶装置 Expired - Fee Related JP2623257B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62202021A JP2623257B2 (ja) 1987-08-13 1987-08-13 ダイナミック型半導体記憶装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62202021A JP2623257B2 (ja) 1987-08-13 1987-08-13 ダイナミック型半導体記憶装置

Publications (2)

Publication Number Publication Date
JPS6446291A true JPS6446291A (en) 1989-02-20
JP2623257B2 JP2623257B2 (ja) 1997-06-25

Family

ID=16450608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62202021A Expired - Fee Related JP2623257B2 (ja) 1987-08-13 1987-08-13 ダイナミック型半導体記憶装置

Country Status (1)

Country Link
JP (1) JP2623257B2 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100413065B1 (ko) * 2001-01-04 2003-12-31 삼성전자주식회사 반도체 메모리 장치의 비트 라인 부스팅 커패시터의 배치구조
JP2006209957A (ja) * 2005-01-28 2006-08-10 Samsung Electronics Co Ltd 信号線の電圧等化及びプリチャージ回路とその動作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160888A (ja) * 1983-03-01 1984-09-11 Nec Corp ビツト線プリチヤ−ジ方式

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160888A (ja) * 1983-03-01 1984-09-11 Nec Corp ビツト線プリチヤ−ジ方式

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100413065B1 (ko) * 2001-01-04 2003-12-31 삼성전자주식회사 반도체 메모리 장치의 비트 라인 부스팅 커패시터의 배치구조
JP2006209957A (ja) * 2005-01-28 2006-08-10 Samsung Electronics Co Ltd 信号線の電圧等化及びプリチャージ回路とその動作方法

Also Published As

Publication number Publication date
JP2623257B2 (ja) 1997-06-25

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