JPS6444734U - - Google Patents
Info
- Publication number
- JPS6444734U JPS6444734U JP13814987U JP13814987U JPS6444734U JP S6444734 U JPS6444734 U JP S6444734U JP 13814987 U JP13814987 U JP 13814987U JP 13814987 U JP13814987 U JP 13814987U JP S6444734 U JPS6444734 U JP S6444734U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- comparator
- synchronization pattern
- output
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007423 decrease Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Description
第１図は本考案によるフレーム同期保護回路の
一実施例を示す概略構成図、第２図は第１図の実
施例の動作状態を表わすタイミング図、第３図は
従来のフレーム同期保護回路を表わす概略構成図
である。
２６……同期パターン検出器、２７……アツプ
ダウンカウンタ、３２……第１のコンパレータ、
３５……フリツプフロツプ、３６……第２のコン
パレータ、３９……アンド回路。
FIG. 1 is a schematic configuration diagram showing an embodiment of the frame synchronization protection circuit according to the present invention, FIG. 2 is a timing diagram showing the operating state of the embodiment of FIG. 1, and FIG. FIG. 26... Synchronization pattern detector, 27... Up-down counter, 32... First comparator,
35...Flip-flop, 36...Second comparator, 39...AND circuit.
Claims (1)
を含むフレーム構造を有する入力デイジタル信号
の中でフレーム同期パターンからあるビツト数ま
で異なつていても予め定めた判定閾値内としてフ
レーム同期信号と判定する同期パターン検出器と
、この同期パターン検出器の出力である一致信号
が入力されると計数を減じ、不一致信号が入力さ
れると計数を増すアツプダウンカウンタと、この
アツプダウンカウンタの計数値がある所定の価Ｍ
１以上であることを判定する第１のコンパレータ
と、他のある所定の価Ｍ２（Ｍ１＞Ｍ２）以下で
あることを判定する第２のコンパレータと、前記
第１のコンパレータの出力によりセツトされるフ
リツプフロツプと、前記第２のコンパレータの出
力によりリセツトされるフリツプフロツプと、こ
のフリツプフロツプからの出力と前記不一致信号
との論理積をとり、ハンテイングパルスを生成す
るアンド回路とを具備し、前記同期パターン検出
器は前記第１および第２のコンパレータの出力に
基づいて前記判定閾値を変化させることができる
ことを特徴としたＰＣＭ再生装置におけるフレー
ム同期保護回路。 Synchronization pattern detection that determines a frame synchronization signal within a predetermined determination threshold even if the input digital signal has a frame structure including a frame synchronization pattern composed of multiple bits, even if the signal differs by a certain number of bits from the frame synchronization pattern. an up-down counter that decreases the count when a coincidence signal, which is the output of this synchronization pattern detector, is input, and increases the count when a mismatch signal is input, and a predetermined value with the count value of this up-down counter M
A first comparator that determines that the value is 1 or more, a second comparator that determines that the value is less than or equal to some other predetermined value M 2 (M 1 >M 2 ), and the output of the first comparator a flip-flop that is set, a flip-flop that is reset by the output of the second comparator, and an AND circuit that performs a logical product of the output from the flip-flop and the mismatch signal to generate a hunting pulse; A frame synchronization protection circuit in a PCM playback device, wherein the synchronization pattern detector is capable of changing the determination threshold based on the outputs of the first and second comparators.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13814987U JPS6444734U (en) | 1987-09-11 | 1987-09-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13814987U JPS6444734U (en) | 1987-09-11 | 1987-09-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6444734U true JPS6444734U (en) | 1989-03-17 |
Family
ID=31400221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13814987U Pending JPS6444734U (en) | 1987-09-11 | 1987-09-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6444734U (en) |
-
1987
- 1987-09-11 JP JP13814987U patent/JPS6444734U/ja active Pending
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