JPS6444643A - Multiplexer - Google Patents

Multiplexer

Info

Publication number
JPS6444643A
JPS6444643A JP20209187A JP20209187A JPS6444643A JP S6444643 A JPS6444643 A JP S6444643A JP 20209187 A JP20209187 A JP 20209187A JP 20209187 A JP20209187 A JP 20209187A JP S6444643 A JPS6444643 A JP S6444643A
Authority
JP
Japan
Prior art keywords
order group
signal
buffer memory
ais
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20209187A
Other languages
Japanese (ja)
Other versions
JPH071881B2 (en
Inventor
Masahiro Shinbashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20209187A priority Critical patent/JPH071881B2/en
Publication of JPS6444643A publication Critical patent/JPS6444643A/en
Publication of JPH071881B2 publication Critical patent/JPH071881B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To secure the normal operation of a buffer memory by directly writing an AIS signal in the buffer memory in case of no input of a lower-order group signal or a higher-order group signal. CONSTITUTION:A lower-order group oscillator 216 which controls the AIS signal frequency is provided, and an AIS converter 217 to which an input break detection signal (i) sent from an input break detector 214 is connected is inserted to the preceding stage of a buffer memory 212, and this converter 217 outputs a write clock (b) corresponding to the output clock of the lower-order group oscillator 216 and lower-order group data (AIS signal) (c) of all '1' when input break is detected. Lower-order group data (c) is written in the buffer memory 212 in accordance with the write clock (b) when a lower-order group signal (a) is inputted, and the AIS signal of all '1' is written there in accordance with the output clock of the lower-order group oscillator 216 when this input is broken.
JP20209187A 1987-08-13 1987-08-13 Multiplexing device Expired - Fee Related JPH071881B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20209187A JPH071881B2 (en) 1987-08-13 1987-08-13 Multiplexing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20209187A JPH071881B2 (en) 1987-08-13 1987-08-13 Multiplexing device

Publications (2)

Publication Number Publication Date
JPS6444643A true JPS6444643A (en) 1989-02-17
JPH071881B2 JPH071881B2 (en) 1995-01-11

Family

ID=16451817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20209187A Expired - Fee Related JPH071881B2 (en) 1987-08-13 1987-08-13 Multiplexing device

Country Status (1)

Country Link
JP (1) JPH071881B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352344A (en) * 1989-07-19 1991-03-06 Fujitsu Ltd Dsc interface for radio equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0352344A (en) * 1989-07-19 1991-03-06 Fujitsu Ltd Dsc interface for radio equipment

Also Published As

Publication number Publication date
JPH071881B2 (en) 1995-01-11

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees