JPS6444637U - - Google Patents

Info

Publication number
JPS6444637U
JPS6444637U JP13883887U JP13883887U JPS6444637U JP S6444637 U JPS6444637 U JP S6444637U JP 13883887 U JP13883887 U JP 13883887U JP 13883887 U JP13883887 U JP 13883887U JP S6444637 U JPS6444637 U JP S6444637U
Authority
JP
Japan
Prior art keywords
hole
protrusion
sealing frame
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13883887U
Other languages
Japanese (ja)
Other versions
JPH0452997Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987138838U priority Critical patent/JPH0452997Y2/ja
Publication of JPS6444637U publication Critical patent/JPS6444637U/ja
Application granted granted Critical
Publication of JPH0452997Y2 publication Critical patent/JPH0452997Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例に係る半導体装置の断
面図、第2図はその半導体装置に用いられるリー
ドピンの拡大側面図、第3図ならびに第4図はそ
の半導体装置の組立順序の一部を説明するための
断面図、第5図ならびに第6図はリードピンの変
形例を示す正面図ならびに側面図、第7図は従来
の半導体装置の断面図である。 1……プリント基板、2……ICチツプ、3…
…導電層、4……封止枠体、5……ボンデイグワ
イヤ、6……合成樹脂、7……キヤツプ、8……
リードピン、9……第1環状突部、10……第2
環状突部、11……第1透孔、12……第2透孔
、16……突出部。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged side view of a lead pin used in the semiconductor device, and FIGS. 3 and 4 are part of the assembly sequence of the semiconductor device. 5 and 6 are front and side views showing modified examples of lead pins, and FIG. 7 is a sectional view of a conventional semiconductor device. 1...Printed circuit board, 2...IC chip, 3...
...Conductive layer, 4... Sealing frame, 5... Bonding wire, 6... Synthetic resin, 7... Cap, 8...
Lead pin, 9...first annular protrusion, 10...second
Annular protrusion, 11...first through hole, 12...second through hole, 16...protrusion.

Claims (1)

【実用新案登録請求の範囲】 (1) 半導体素子を搭載したプリント基板上に封
止枠体を載置し、その封止枠体の開口部内に樹脂
を注入して固化することにより前記半導体素子を
封止する構造の半導体装置において、 前記封止枠体ならびにプリント基板に、両者を
重合した際に互いに連通する第1の透孔ならびに
第2の透孔をそれぞれ形成し、その封止枠体に設
けられた第1の透孔よりも外寸が若干大きい第1
の突部と、前記プリント基板に設けられた第2の
透孔よりも外寸が若干大きい第2の突部とをリー
ドピンにそれぞれ設け、そのリードピンを封止枠
体とプリント基板の透孔に圧入することにより、
前記第1の突部を第1の透孔内周部に食い込ませ
、第2の突部を第2の透孔内周部に食い込ませて
、そのリードピンによつて封止枠体とプリント基
板とを一体に連結したことを特徴とする半導体装
置。 (2) 実用新案登録請求の範囲第(1)項記載におい
て、前記第1の突部ならびに第2の突部が環状突
部であることを特徴とする半導体装置。 (3) 実用新案登録請求の範囲第(1)項または第(2
)項記載において、前記第2の突部のピン周面か
らの突部長さが、第1の突部のピン周面からの突
出長さより短かいことを特徴とする半導体装置。 (4) 実用新案登録請求の範囲第(1)項記載におい
て、前記リードピンが複数列設されてリードピン
列を構成し、そのリードピン列が前記半導体素子
を間にして対向していることを特徴とする半導体
装置。 (5) 実用新案登録請求の範囲第(1)項記載におい
て、前記封止枠体とプリント基板が同じ材質のも
のから構成されていることを特徴とする半導体装
置。
[Claims for Utility Model Registration] (1) A sealing frame is placed on a printed circuit board on which a semiconductor element is mounted, and a resin is injected into the opening of the sealing frame and solidified. In a semiconductor device having a structure for sealing, the sealing frame and the printed circuit board are each formed with a first through hole and a second through hole that communicate with each other when both are superposed, and the sealing frame is sealed. The first through hole is slightly larger in outer size than the first through hole provided in the first through hole.
and a second protrusion that is slightly larger in outer size than the second through hole provided in the printed circuit board, respectively, are provided on the lead pin, and the lead pin is inserted into the through hole of the sealing frame and the printed circuit board. By press-fitting,
The first protrusion bites into the inner periphery of the first through hole, the second protrusion bites into the inner periphery of the second through hole, and the sealing frame and the printed circuit board are connected by the lead pins. A semiconductor device characterized by being integrally connected. (2) Utility Model Registration The semiconductor device according to claim (1), wherein the first protrusion and the second protrusion are annular protrusions. (3) Scope of claims for utility model registration, paragraph (1) or (2)
3.) The semiconductor device according to item 1, wherein a length of the second protrusion extending from the circumferential surface of the pin is shorter than a length of the first protrusion protruding from the circumferential surface of the pin. (4) Utility model registration Claim (1), characterized in that the lead pins are provided in a plurality of rows to form a lead pin row, and the lead pin rows face each other with the semiconductor element in between. semiconductor devices. (5) The semiconductor device according to claim (1) of the utility model registration, characterized in that the sealing frame and the printed circuit board are made of the same material.
JP1987138838U 1987-09-12 1987-09-12 Expired JPH0452997Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987138838U JPH0452997Y2 (en) 1987-09-12 1987-09-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987138838U JPH0452997Y2 (en) 1987-09-12 1987-09-12

Publications (2)

Publication Number Publication Date
JPS6444637U true JPS6444637U (en) 1989-03-16
JPH0452997Y2 JPH0452997Y2 (en) 1992-12-14

Family

ID=31401547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987138838U Expired JPH0452997Y2 (en) 1987-09-12 1987-09-12

Country Status (1)

Country Link
JP (1) JPH0452997Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339191B1 (en) * 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6236541U (en) * 1985-08-20 1987-03-04

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744868A (en) * 1980-08-29 1982-03-13 Fujitsu Ltd Measuring method for magnetostriction constant

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6236541U (en) * 1985-08-20 1987-03-04

Also Published As

Publication number Publication date
JPH0452997Y2 (en) 1992-12-14

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