JPS6444555A - Memory capacity decision system for information processor - Google Patents

Abstract

PURPOSE:To know the existence of memory cards to be easily connected to a bus by means of a simple circuit without increasing the number of bus control lines and having different capacity by validating a bus request (BUS.RQ) line for the memory cards in accordance with a bus control decision signal by utilizing a state that the BUS.RQ line is invalid at the time of initializing. CONSTITUTION:When a processor 1 executes initializing, bus control based upon a bus operation control circuit 6 is executed and an initializing control circuit 7 turns a signal on a signal line (h) to 'true'. Consequently, the memory cards 3-5 are initialized. Simultaneously, the state of signals sent from a memory card searching output circuit 8 to signal lines (f), (g) are changed and the changed signals are inputted to the memory cards 3-5. When the signal on the signal line (f) is 'false' and the signal on the signal line (g) is 'true', memory for 1MB is in the BUS.RQ state. When the signal line (f) is 'true' and the signal on the signal line (g) is 'false', memory for 2MB is in the BUS.RQ state.