JPS6442757A - Input and output interface - Google Patents

Abstract

PURPOSE:To cause data transferring speed to be high by using the hold input of a one-chip microprocessor, establishing an occupational using right between an I/O port data bus and a memory data bus and further, successively designating the address of a memory with an address counter like a hardware. CONSTITUTION:A PCTL 7 of a parallel I/O port is connected to the hold request input of a one-chip microprocessor and a data bus 3a of a parallel I/O port 1 is connected to the data bus of the one-chip microprocessor 3 with a three states bidirectional buffer 10. An address counter 9, which has the PCTL 7 as a trigger, is connected to an address bus and chip select and read/write signals, which are generated in the address counter 9, are connected to a memory 4 with using a selecting circuit. Namely, the access to the memory causes the address of the one-chip microprocessor and the data bus to be in a high impedance condition by the PCTL. The data transferring can be executed at high speed.