JPS6442155A - Semiconductor chip carrier package - Google Patents

Semiconductor chip carrier package

Info

Publication number
JPS6442155A
JPS6442155A JP19827787A JP19827787A JPS6442155A JP S6442155 A JPS6442155 A JP S6442155A JP 19827787 A JP19827787 A JP 19827787A JP 19827787 A JP19827787 A JP 19827787A JP S6442155 A JPS6442155 A JP S6442155A
Authority
JP
Japan
Prior art keywords
pattern
ceramic plate
semiconductor chip
internal
lamination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19827787A
Other languages
Japanese (ja)
Inventor
Shigeru Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19827787A priority Critical patent/JPS6442155A/en
Publication of JPS6442155A publication Critical patent/JPS6442155A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To prevent a lamination defect due to lack of adhesion at a lamination interface of a ceramic plate without requiring the introduction toward a lateral pattern using the lamination interface of the ceramic plate, by introducing an internal pattern to the rear pattern by a through hole pattern. CONSTITUTION:A semiconductor chip carrier package has a through hole pattern 15 penetrating a ceramic plate in a direction of thickness for introducing an internal pattern to a rear pattern. More specifically, a semiconductor chip 10 is connected to an internal pattern 14 formed on the inside surface of the ceramic plate and the internal pattern 14 is connected to the rear pattern 16 of the ceramic plate through the through hole pattern 15 penetrating the ceramic pattern. Therefore, the internal pattern is not introduced through the lamination interface of the ceramic plate, airtight defect is not generated in the lamination portion of the ceramic plate constituting a sidewall of a package.
JP19827787A 1987-08-10 1987-08-10 Semiconductor chip carrier package Pending JPS6442155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19827787A JPS6442155A (en) 1987-08-10 1987-08-10 Semiconductor chip carrier package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19827787A JPS6442155A (en) 1987-08-10 1987-08-10 Semiconductor chip carrier package

Publications (1)

Publication Number Publication Date
JPS6442155A true JPS6442155A (en) 1989-02-14

Family

ID=16388449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19827787A Pending JPS6442155A (en) 1987-08-10 1987-08-10 Semiconductor chip carrier package

Country Status (1)

Country Link
JP (1) JPS6442155A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0550731U (en) * 1991-12-05 1993-07-02 オリジン電気株式会社 Insulating substrate, semiconductor device and circuit device using the same
JP2000183230A (en) * 1998-12-17 2000-06-30 Kyocera Corp Mounting structure for high-frequency circuit package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0550731U (en) * 1991-12-05 1993-07-02 オリジン電気株式会社 Insulating substrate, semiconductor device and circuit device using the same
JP2000183230A (en) * 1998-12-17 2000-06-30 Kyocera Corp Mounting structure for high-frequency circuit package

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