JPS6439054A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6439054A
JPS6439054A JP62194875A JP19487587A JPS6439054A JP S6439054 A JPS6439054 A JP S6439054A JP 62194875 A JP62194875 A JP 62194875A JP 19487587 A JP19487587 A JP 19487587A JP S6439054 A JPS6439054 A JP S6439054A
Authority
JP
Japan
Prior art keywords
epitaxial layer
breakdown strength
linear transistor
type
embedded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62194875A
Other languages
Japanese (ja)
Inventor
Toshiyuki Okoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62194875A priority Critical patent/JPS6439054A/en
Publication of JPS6439054A publication Critical patent/JPS6439054A/en
Pending legal-status Critical Current

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  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To integrate a linear transistor characterized by high breakdown strength, a linear transistor characterized by an excellent saturation voltage characteristic and low breakdown strength and a high speed IIL on the same substrate, by adopting a two-stage epitaxial structure. CONSTITUTION:A P-type first epitaxial layer 22 is formed on a substrate 21. An N-type second epitaxial layer 23 is formed on the first epitaxial layer 22. An N<+> type first embedded layer 24 is formed on the surface of the substrate 21 through the first 1 epitaxial layer 22 so that the boundary is brought into contact with the second epitaxial layer 23. N<+> type second embedded layers 26 are formed on the first epitaxial layer 22. A linear transistor 25 characterized by high breakdown strength is formed on the surface of the second epitaxial layer 23 at a region, where only the first embedded layer 24 is provided. A linear transistor characterized by low breakdown strength and an IIL 28 are formed on the surface of the second epitaxial layer 23 in the regions, where the second embedded layers 26 are provided. Thus the N-P-N linear transistor with high breakdown strength, the N-P-N linear transistor with low breakdown strength and the high speed IIL can be made to coexist.
JP62194875A 1987-08-04 1987-08-04 Semiconductor integrated circuit Pending JPS6439054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62194875A JPS6439054A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62194875A JPS6439054A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6439054A true JPS6439054A (en) 1989-02-09

Family

ID=16331764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62194875A Pending JPS6439054A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6439054A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0461268A (en) * 1990-06-28 1992-02-27 Sanyo Electric Co Ltd Integrated circuit device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0461268A (en) * 1990-06-28 1992-02-27 Sanyo Electric Co Ltd Integrated circuit device and manufacture thereof

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