JPH0461268A - Integrated circuit device and manufacture thereof - Google Patents

Integrated circuit device and manufacture thereof

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Publication number
JPH0461268A
JPH0461268A JP2171522A JP17152290A JPH0461268A JP H0461268 A JPH0461268 A JP H0461268A JP 2171522 A JP2171522 A JP 2171522A JP 17152290 A JP17152290 A JP 17152290A JP H0461268 A JPH0461268 A JP H0461268A
Authority
JP
Japan
Prior art keywords
region
base region
transistor
conductivity type
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2171522A
Other languages
Japanese (ja)
Other versions
JPH07123140B2 (en
Inventor
Teruo Tabata
田端 輝夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2171522A priority Critical patent/JPH07123140B2/en
Publication of JPH0461268A publication Critical patent/JPH0461268A/en
Publication of JPH07123140B2 publication Critical patent/JPH07123140B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To extend the base width of a large signal transistor and to control its hFE to be smaller than hFE of a small signal transistor and a suitable value by forming a low concentration base region having a lower impurity concentration than that of the base region in the bottom of the base region of a large signal transistor having a relatively high impurity concentration. CONSTITUTION:A well region 23 and a low concentration base region 28 of a large signal transistor 25 are simultaneously formed. The entire region 28 is so superposed as to be covered with a base region 26. Since the transistor 25 has the region 26 and the region 28 under an emitter region 27, its impurity concentration profile has inclinations of two stages of a relatively abrupt slope to be formed of the region 26 of a relatively high impurity concentration and a smooth slope to be formed of the region 28 of a relatively low impurity concentration.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 才発明はICmaxと耐Bリーh、v−を全て゛満足I
得るトラシミ5゛スタを只備シイ)1!、導体集積回路
に関する。
Detailed Description of the Invention (a) The invention satisfies all of ICmax and B-resistance h and v- in the field of industrial application.
You can get 5 Stars) 1! , relating to conductor integrated circuits.

(ロ)従来の技術 半導体集積回路eは各拡散領域を共通i=用い−rXL
程を簡略化号”る、−2、が基本的な技術思想−r゛あ
るので、各回路素子は全で共通の拡散領域1”こ構成さ
れ、同・ブップ、fの素子゛(NPN l−ラ′、S、
・スタ)は全で同一・の特性を有(、r::いた。
(b) The conventional technology semiconductor integrated circuit e uses each diffusion region in common i=−rXL
Since there is a basic technical idea -r, which simplifies the equation, each circuit element is composed of a common diffusion region 1, and an element of f (NPN l). -La', S,
・Star) had the same characteristics in all (, r::.

ところが、民生用、特に合°響用IC%−て゛は、各種
信号処理用回路と同時に出力段のバ′、ノー系トランジ
スタが組み込まれることが多く、回路的な要求から前記
信号処理用の小信号トラ)・ジスタと前記出力段用の大
信号ト・ランタスタとで11流増幅率h□を異ならしめ
る要求がある。つまり、小信号トランジスタのh□を1
00〜200とし、た時に、大信号トランジスタのり、
を50程度に下げて:G人−ルクタ電流Iemaxを増
大jるという要求である。
However, ICs for consumer use, especially for acoustics, often incorporate output stage transistors and output stage transistors at the same time as various signal processing circuits, and due to circuit requirements, small signals for signal processing are There is a demand for making the 11-stream amplification factor h□ different between the transistor (transistor) transistor and the large signal transistor transistor for the output stage. In other words, the h□ of the small signal transistor is 1
00 to 200, when large signal transistor glue,
This is a request to lower G to about 50 and increase the G-actor current Iemax.

この」うにh□を変更を−る手段とじ−で、−1例えば
特開昭60−7075653′公報に記載されτ゛いる
ようにベース領域を個々に別形成す2.手段がある。
By means of changing h□ in this way, -1. For example, the base regions can be formed separately as described in Japanese Patent Application Laid-Open No. 60-7075653'. There is a means.

即ち第3図に示す如く、エビタ4ジャルJ!!(1)を
分離領域<2)で分離し7た各アイランド(3)に、小
信号トランジスタ(4)用のベース領域(5)と大信号
トランジスタ(6)用のベース領域(7)とを個々に形
成するものである。この時、大信号トランジスタ(6)
のベース領域(7)は2つの手法が考えられる。
That is, as shown in Figure 3, Evita 4 Jal J! ! A base region (5) for a small signal transistor (4) and a base region (7) for a large signal transistor (6) are provided in each island (3) obtained by separating (1) by an isolation region < 2. They are formed individually. At this time, large signal transistor (6)
Two methods can be considered for the base region (7).

1つは不純物濃度を高く設定してh□を小さくする手法
(第4図第1案)、2つは拡散深さを深くして(ベース
幅を広げる)h□を小さくする手法(第4図第2案)で
ある。
One is to set the impurity concentration high to reduce h□ (Fig. 4, plan 1), and the second is to deepen the diffusion depth (widen the base width) to reduce h□ (Fig. 4, plan 1). Fig. 2 draft).

(八)発明が解決しようとする!#!題しかしながら、
上記先の手法はシリコン結晶に対するボロンの飽和限界
があるためにそれ程高くはできず、従ってh□を下げる
にも限界があるという欠点があった。しかもツェナ降伏
による耐圧劣化が危惧される他、ベース領域(7)をイ
オン注入で形成する場合はドーズ量が増ず分処理時間が
長くな−> ”TT ’、Il程の煩雑化を招く。他づ
)、後の手法Jet h□をトげるというVJ的には合
致す゛ろが、不純物a度と拡散深さとは密接な関係があ
り、ベースのイ〈鈍物濃度が低下して伝導度変調をきた
ψ−ので、Iemaxが増大し、ないという欠点があン
た。この、−とから、h□が同じであればベースの濃度
は高い力が1.eaiaxを大きくできるのて二ある。
(8) Invention tries to solve! #! However,
The above-mentioned method had the disadvantage that it could not be made that high because of the saturation limit of boron with respect to silicon crystal, and therefore there was a limit to lowering h□. Moreover, in addition to the fear of breakdown voltage deterioration due to Zener breakdown, when the base region (7) is formed by ion implantation, the dose amount increases and the processing time becomes longer, resulting in complications such as ``TT'' and Il. Although the latter method is consistent with VJ in that it increases Jet Since ψ-, which caused ψ-, Iemax increases, and the disadvantage of not having it is eliminated.From this -, if h□ is the same, the concentration of the base is 1, which can increase eaiax.2.

そし。stop.

1−1不純物濃度とベース幅の両者を制御したとしても
、hFI!とICmaxの両者を満足させることはやは
り困難であった。
1-1 Even if both the impurity concentration and base width are controlled, hFI! It was still difficult to satisfy both of ICmax and ICmax.

り二)課題を解決するための手段 本発明は上記従来の欠点に鑑み成され、比較的高い不純
物濃度を有する大信号ト・ランジスタ(25)のベース
領域(26)の底部に、ベース領域(26)よりは低い
不純物濃度を有する低濃度ベース領域(28)を形成す
ることにより、小信号トランジスタ(16)よりは小さ
いh□を有する大信号トランジスタ(2りを共存させる
と共に、前記低濃度ベース領域(28)とI I L(
20)のウェル領域(23)とを同時形成することによ
り、IILとの共存をも図るものである。
2) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks of the conventional art. By forming a low concentration base region (28) having an impurity concentration lower than that of the small signal transistor (16), a large signal transistor (28) having an impurity concentration lower than that of the small signal transistor (16) can coexist, and Area (28) and I I L (
Coexistence with IIL is also attempted by forming the well region (23) of 20) at the same time.

(*)作用 本発明によれば、低a11I−ベース領域(28)苓重
畳したことによっ[大信号トニシンジスタク25)のべ
、4幅が広がるので、そのり、を小値17j、 lう〕
・シーズ、夕(16)のす、□より小さく11つ適切な
値に制御4′ビ)ことかてごきる。しかも、ベースの一
部は比較的高い不純物濃度を有4−゛るベース領域〈2
6)で構成、#るので、最大ニアし・フタt ′t1t
Icmazを大にできる。そして、前記大信11ランジ
スタ(25)の低濃度べ9ス領域り28)をI I L
(2O)の低濃度つ、ル領域(23〉と同時形成4るの
で、効率的に共存させるこ8とができる。
(*) Effect According to the present invention, by superimposing the low a11I-base region (28), the width of the large signal (25) is expanded, so the small value 17j, l)
- Seeds, evening (16), □ to an appropriate value of 11 smaller than 4' Bi). Moreover, a part of the base is a 4-゛ base region with a relatively high impurity concentration.
6) Since it is composed of #, the maximum nearness and lid t 't1t
You can increase Icmaz. Then, the low concentration base area 28) of the Daishin 11 transistor (25) is
Since the low concentration of (2O) is formed at the same time as the region (23), they can coexist efficiently.

(へ)実施例 以下に本発明の一実施例を図面を参照し、ながら詳細に
説明する。
(F) Example An example of the present invention will be described below in detail with reference to the drawings.

第1図は本発明による半導体集積回路を示ず゛断面図で
ある。同図においし、(11)はP型’)す”ノン甲、
結晶基板、(12)は基板(11)表面に丁−ビ成長シ
、18形成したN−型14ビタキシャル層、(13)け
N7,91埋め込み層、(14)は埋め込み!’Pi 
(13)を囲みjF°々キシャル層(12)を貫通すビ
)P +型分離領域、(I5)は分離領域(14)によ
っr’′個々(ご分離されたアイ:テ〉ドであ6゜ アイランド(15)の1つ番こは小侶叶1−7)ジスタ
(16〉を形成4゛−くP型のベース領域(17)、!
= N″型のゴーミッタ領域(18)を形成し、アイ−
7〉ド(15)を:口、・フタとして縦型NPNトラン
ジスタを形成する。(19)はN′型二y Lクター]
ンタ/7)・領域で=ある。
FIG. 1 is a sectional view, not showing a semiconductor integrated circuit according to the present invention. In the same figure, (11) is P-type ')' non-A,
Crystal substrate, (12) is an N-type 14 bitaxial layer grown on the surface of the substrate (11), (18) is formed, (13) is an N7,91 buried layer, and (14) is buried! 'Pi
A bi) P + type separation region surrounding (13) and penetrating through the axial layer (12), (I5) is separated by the separation region (14) with One of the 6゜ islands (15) is the 4゛-P-shaped base region (17), which forms the small leaf 1-7) jista (16〉)!
= N″ type gomitter region (18) is formed, and the eye-
7> A vertical NPN transistor is formed using the dots (15) as the opening and lid. (19) is N' type 2y L vector]
/7)・area==.

他のアイ−7> )’(15)にはI I L(20>
を形成ジべくP型のインジェクタ領域(21)と外部ベ
ース領域(22)、P”型のウェル領域<23)、N+
型の:IL・フタ領域(24)を形成(7、つ、ル領域
(23)を逆方゛向縦型インバータ)・ランジスタのベ
ースとし一1’11 Lを形成する。つ、ル領域(23
)をベースとすることにより、前記インバータトランジ
スタの−1ミツタからベース・\のキャリ?注入の主体
2−なるN”型埋め込み層(13)にベースが近接する
ので、高い逆βが得られるというものである。
Other I-7>)'(15) has I I L(20>
In order to form a P-type injector region (21) and an external base region (22), a P”-type well region <23), N+
Mold: Form an IL/lid area (24) (7. Use the IL/lid area (23) as a base for a reverse direction vertical inverter) and form a transistor 1'11L. Two areas (23
) as the base, the carry of the base \ from -1 mitter of the inverter transistor? Since the base is close to the N'' type buried layer (13) which is the main body of implantation 2-, a high inverse β can be obtained.

EL、t\史に他のアイランド(15)には大信汀]・
う・〕・・レスタ(25〉夕、形成すべくP型へ− ス
領域(26)とN”型1−丁ミッタ領域(27)を形成
する他、べ〜ス領域(26〉に重ね丁−P−型の低濃度
ベース領域(28)を形成した。り29・)はN4コt
・り々コンタク]・領域、(30)はS/り丁7〉酸化
膜、(31)は各電極Cある。ベース領域(1,7>(
26)と、ゴーミッタ領域(IU(27)は夫々共通の
工程で形成し、た。また、I I 1.、(2O)のウ
ェル領域り23)と大信号トラ〉・ジスタ(25)の低
濃度ベース領域(28)は同時形成した。
EL, t\ History and other islands (15) are Daishin Tei]・
U.]...Resta (25〉 evening) In addition to forming a P-type base area (26) and an N'' type 1-chomitter area (27), a layered plate was added to the base area (26〉). -P- type low concentration base region (28) was formed.
・Riricontact]・area, (30) is the S/R 7〉 oxide film, and (31) is each electrode C. Base region (1,7>(
26) and the gomitter region (IU (27)) were formed in the same process. Also, the well region (23) of II1., (2O) and the low voltage transistor (25) of the large signal transistor The concentration base region (28) was formed at the same time.

IILのウェル領域(23)は、前述し、た、!うにベ
ース・1ミッタ接合を埋め込み層(13)に近接するこ
とが目的であるから、拡散深さは深く、且つ逆βを高く
する為に低不純物濃度としである。具体的には、ベース
領域(17)(26)が表面濃度1011011ato
σ−1、拡散深さ1.0〜1.5μに形成されるのに対
し、ウェル領域(23)は表面濃度10′1〜1、0 
Ita、toms−crri−”、拡散深さ2.0〜3
.0μに形成する。
The IIL well region (23) is as described above. Since the purpose is to bring the base-1-mitter junction close to the buried layer (13), the diffusion depth is deep and the impurity concentration is low in order to increase the inverse β. Specifically, the base regions (17) and (26) have a surface concentration of 1011011ato
σ-1, with a diffusion depth of 1.0-1.5μ, whereas the well region (23) has a surface concentration of 10′1-1,0.
Ita, toms-cri-”, diffusion depth 2.0-3
.. Formed to 0μ.

ウェル領域(23)と大信号トランジスタ(25)の低
a度・\ ス領域(28)とは同時形成するので、低濃
度・ベース領域(28)は当然にL記1.たイζ純物濃
度と深さをイイする。、このようにイ・鈍物濃度を低く
[また場合、不純物の表面デプリート・にょろり−”I
tの増スが危惧されるので、低濃度ベー ス領域(28
)はベース領域〈26)をはみ出さないように形成した
。−、、)1す、低濃度ベース領域(28)の全面をヘ
ス領域(26)T覆うように重畳したのである。
Since the well region (23) and the low-a degree / low concentration region (28) of the large signal transistor (25) are formed at the same time, the low concentration / base region (28) is naturally formed as described in L.1. The purity concentration and depth should be selected. , In this way, the concentration of dull substances can be lowered [In addition, if the surface depletion of impurities is
Since there is a concern that t may increase, the low concentration base region (28
) was formed so as not to protrude from the base region <26). -,,)1, the low concentration base region (28) is overlapped so as to cover the entire surface of the Hess region (26)T.

大信号]ランジスタ(25)は、エミッタ領域(27)
のF部にベース領域(26)と低濃度べ・−ス領域(2
8)とを有4るので、その不純物濃度ブL1ファイルは
第5図に丞すような分布を有する。即ち、比較的高不純
物濃度のベース領域(26)が形成する比較的急峻な傾
きと、比較的低不純物濃度の低濃度ベース領域(28)
が形成する緩やかな傾きとの2段階の傾きを有する。結
果、大信号トランジスタ(25)のベース幅W、は同図
に示す如く低濃度ベース領域(28〉の拡散深さで決ま
るので、ベース領域〈26)だけの小信号トランジスタ
(17)よりはベース幅を大にでき、を流増幅率り。を
小にできる。低不純物濃度の領域であるから、h□が十
゛かり過ぎるJいうことも無い。と同時に、大信号(・
う)ジスタく25〉のベースにはベース拡散による比較
的高不純物濃度のベース領域(26)が重なるので、ベ
ースの伝導度変調による影響が少なく、従ってhywを
下げたことにより得られるIemaxの増大を最大限有
効に引き出tことができる。
Large signal] The transistor (25) is the emitter region (27)
A base region (26) and a low concentration base region (2
8) and 4, the impurity concentration L1 file has a distribution as shown in FIG. That is, the relatively steep slope formed by the base region (26) with a relatively high impurity concentration, and the low concentration base region (28) with a relatively low impurity concentration.
It has two levels of slope: a gentle slope formed by . As a result, the base width W of the large signal transistor (25) is determined by the diffusion depth of the low concentration base region (28) as shown in the same figure, so the base width W of the large signal transistor (25) is determined by the diffusion depth of the low concentration base region (28), so the base width W of the large signal transistor (25) is determined by the diffusion depth of the low concentration base region (28). The width can be increased, and the current amplification rate can be increased. can be made small. Since this is a region of low impurity concentration, there is no need for h□ to be too large. At the same time, a large signal (・
c) Since the base of the transistor 25 overlaps with the base region (26) with a relatively high impurity concentration due to base diffusion, there is little influence from conductivity modulation of the base, and therefore the increase in Iemax obtained by lowering hyw. can be extracted as effectively as possible.

第2図A乃至第2図りは本願集積回路の製造方法を示し
た。
FIGS. 2A to 2D illustrate a method of manufacturing the integrated circuit of the present invention.

先ず第2図Aに示す如く埋め込み層〈13)と1側の分
離領域(14)を形成した基板(11)上にエピタキシ
ャル層<12)を形成し、ボロン(B)を低濃度ベース
領域(28)とつLル領域(23)に対応する部分に選
択的に必要なドーズ量だけイオン注入し、第2図Bに示
す通り基板(11)全体に熱処理を加えることによりエ
ピタキシャル層(12)表面にドープしたボロン(B、
)を所望深さまで1ライブインをし、 第2図Cに示j通り上側の分離領域〈14)を形成した
後、再びボr1ン(B)を選択的にイオン注入してドラ
イブインゆ−る、−とに、より小信号トう〉・シースタ
フ16)のベース領域(17)と犬信M(・;アンジス
タ〈?5)のベース領域(27)、I I L(2,、
Q)の外部△、・−・ス領域り22)とイ〉シ゛エクタ
領域(21)とを全て同時形成し、 そして第2図りに示す通り、1〜ミツタ拡散で小信号ト
ランジスタ(16)と大信号トランジスタ(25)のエ
ミッタ領域(18)(27)、およびI I L(gQ
)の″−ルクタ領域(24)を形成する。
First, as shown in FIG. 2A, an epitaxial layer <12) is formed on a substrate (11) on which a buried layer <13) and one side isolation region (14) are formed, and boron (B) is added to a low concentration base region (14). 28) The epitaxial layer (12) is formed by selectively implanting ions at a required dose into the portion corresponding to the L region (23) and heat-treating the entire substrate (11) as shown in FIG. 2B. Boron doped on the surface (B,
) to a desired depth to form an upper isolation region (14) as shown in FIG. The base region (17) of the small signal To〉 Sea Stuff 16) and the base region (27) of Inushin M (・; Angister〈?5), I I L (2,,
The external △, . The emitter regions (18) (27) of the signal transistor (25), and I I L (gQ
) to form a ``-lucta region (24).

本願構成は、多少の熱処理を加えても拡散深さが変動し
てくい、拡散済みの低濃度ベース領域く28)にベース
拡散を処して小信号トランジスタ(坊)と大信号トラン
ジスタ(25)を形成するので、ベース拡散は小信号ト
ランジスタ(16)用に制御して拡散を行うことができ
る。従って、小信号トランジスタ(16)、大信号トラ
ンジスタ(μs)共に特性の制御が極めて容易である。
In the configuration of the present invention, the diffusion depth does not change even if a certain amount of heat treatment is applied, and base diffusion is performed on the already diffused low concentration base region 28) to form a small signal transistor (bo) and a large signal transistor (25). Since the base diffusion is formed, a controlled diffusion can be performed for the small signal transistor (16). Therefore, it is extremely easy to control the characteristics of both the small signal transistor (16) and the large signal transistor (μs).

(ト)発明の効果 以上に説明した通り、本発明によれば、大信号トランジ
スタ〈25)に低濃度ベース領域(28)を重ねること
によって、h□が高い小信号トランジスタ(16)とり
、が小さい大信号トランジスタ(25)とを界易に共存
できる利点を山−する。また、大信号トランジスタフ2
5)のベースは比較的高い不純物濃度を有Jるベース領
域(26)との重畳であるから、伝導度変調によるIe
maxの低下が少なく、従って1co+axを最大限に
増大できる利点を有4“る。さらに、大信号トランジス
タ(25〉のり、をFげることによっでASOを増大せ
しめ、出力段トランジスタとして適切な特性に製造でき
る利点をも有1−る。そして更に、低濃度ベース領域(
28)を利用することによって、大信号、小信号共に特
性の制御が容易であるという利点をも有する。
(g) Effects of the Invention As explained above, according to the present invention, by overlapping the low concentration base region (28) on the large signal transistor (25), the small signal transistor (16) with high h It has the advantage of being able to easily coexist with a small large signal transistor (25). Also, large signal transistor 2
Since the base of 5) overlaps with the base region (26) having a relatively high impurity concentration, Ie due to conductivity modulation
It has the advantage that the drop in max is small and therefore 1co+ax can be maximized.Furthermore, by increasing the large signal transistor (25〉), the ASO can be increased, making it suitable as an output stage transistor. It also has the advantage of being able to be manufactured with specific characteristics.In addition, the low concentration base region (
28) has the advantage that the characteristics of both large and small signals can be easily controlled.

そしてさらに、大信号トランジスタ<25)の低濃度ベ
ース領域(28)はI I L(20)のウェル領域〈
23)と共用するので、特に製造工程を増大すること無
く3種類の素子を共存できるという利点をも有する。
Furthermore, the low concentration base region (28) of the large signal transistor <25) is the well region of I I L (20)
23), it also has the advantage that three types of elements can coexist without increasing the manufacturing process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を説明するための断面図、第2図A−D
はその製造方法を説明積るための断面図、第3図は従来
例を説明するための断面図、第4図は従来の不純物濃度
分布を示す図、第5図は本願の不純物濃度分布を示1図
である。
Fig. 1 is a sectional view for explaining the present invention, Fig. 2 A-D
3 is a sectional view for explaining the manufacturing method, FIG. 3 is a sectional view for explaining the conventional example, FIG. 4 is a diagram showing the conventional impurity concentration distribution, and FIG. 5 is the impurity concentration distribution of the present application. FIG.

Claims (5)

【特許請求の範囲】[Claims] (1)一導電型の半導体基板の上に形成した逆導電型の
エピタキシャル層と、 前記エピタキシャル層を分離して形成した複数個のアイ
ランドと、 第1のトランジスタを構成するために、第1のアイラン
ドの表面に形成した一導電型のベース領域およびベース
領域表面に形成した逆導電型のエミッタ領域と、 第2のトランジスタを構成するために、第2のアイラン
ドの表面に形成した一導電型のベース領域およびベース
領域表面に形成した逆導電型のエミッタ領域と、 前記第2のトランジスタのベース領域に重ねて形成した
前記ベース領域より深く且つ前記ベース領域よりは低不
純物濃度の低濃度ベース領域と、IILを構成するため
に、第3のアイランドの表面に形成した一導電型のイン
ジェクタ領域、外部ベース領域、逆導電型のコレクタ領
域、および前記第2のトランジスタの低濃度ベース領域
と同時形成したウェル領域とを具備することを特徴とす
る半導体集積回路。
(1) An epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type, a plurality of islands formed by separating the epitaxial layer, and a first transistor to form a first transistor. A base region of one conductivity type formed on the surface of the island, an emitter region of opposite conductivity type formed on the surface of the base region, and a base region of one conductivity type formed on the surface of the second island to form a second transistor. a base region; an emitter region of opposite conductivity type formed on the surface of the base region; and a low concentration base region formed overlapping the base region of the second transistor, which is deeper than the base region and has a lower impurity concentration than the base region. , an injector region of one conductivity type formed on the surface of the third island, an external base region, a collector region of the opposite conductivity type, and a lightly doped base region of the second transistor were formed simultaneously to form the IIL. A semiconductor integrated circuit comprising a well region.
(2)前記第1のトランジスタのベース領域と前記第2
のトランジスタのベース領域と前記IILのインジェク
タ領域および外部ベース領域とを同時形成したことを特
徴とする請求項第1項に記載の半導体集積回路。
(2) the base region of the first transistor and the second transistor;
2. The semiconductor integrated circuit according to claim 1, wherein the base region of the transistor, the injector region and the external base region of the IIL are formed simultaneously.
(3)前記第2のトランジスタは出力用トランジスタを
構成することを特徴とする請求項第1項に記載の半導体
集積回路。
(3) The semiconductor integrated circuit according to claim 1, wherein the second transistor constitutes an output transistor.
(4)前記第2のトランジスタのベース領域は前記低濃
度ベース領域を完全に覆うように重畳することを特徴と
する請求項第1項に記載の半導体集積回路。
(4) The semiconductor integrated circuit according to claim 1, wherein the base region of the second transistor overlaps the low concentration base region so as to completely cover it.
(5)一導電型の半導体基板上に逆導電型のエピタキシ
ャル層を形成する工程、 前記エピタキシャル層の表面に一導電型の不純物をイオ
ン注入し、所望深さに拡散して大信号トランジスタ用の
低濃度ベース領域とIILのウェル領域を形成する工程
、 前記エピタキシャル層の表面に一導電型の不純物を選択
的に拡散し、小信号トランジスタ用のベース領域、前記
大信号トランジスタ用の前記低濃度ベース領域より浅く
これと重畳し前記低濃度ベース領域よりは高い不純物濃
度を有するベース領域、およびIILのインジェクタ領
域と外部ベース領域を形成する工程、 逆導電型の不純物を選択的に導入し、前記小信号トラン
ジスタのベース領域表面にエミッタ領域を、前記大信号
トランジスタの低濃度ベース領域とベース領域とが重畳
する部分にエミッタ領域を、前記IILのウェル領域表
面にコレクタ領域を形成する工程、 とを具備することを特徴とする半導体集積回路の製造方
法。
(5) Forming an epitaxial layer of opposite conductivity type on a semiconductor substrate of one conductivity type, ion-implanting an impurity of one conductivity type into the surface of the epitaxial layer and diffusing it to a desired depth to form a large signal transistor. forming a low concentration base region and an IIL well region, selectively diffusing impurities of one conductivity type into the surface of the epitaxial layer to form a base region for a small signal transistor and a low concentration base for the large signal transistor; forming a base region shallower than the base region and overlapping with the low concentration base region and having an impurity concentration higher than the low concentration base region, and an injector region and an external base region of the IIL; selectively introducing impurities of opposite conductivity type; forming an emitter region on the surface of the base region of the signal transistor, an emitter region in a portion where the low concentration base region of the large signal transistor and the base region overlap, and a collector region on the surface of the well region of the IIL. A method for manufacturing a semiconductor integrated circuit, characterized by:
JP2171522A 1990-06-28 1990-06-28 Method for manufacturing semiconductor integrated circuit Expired - Lifetime JPH07123140B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2171522A JPH07123140B2 (en) 1990-06-28 1990-06-28 Method for manufacturing semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2171522A JPH07123140B2 (en) 1990-06-28 1990-06-28 Method for manufacturing semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPH0461268A true JPH0461268A (en) 1992-02-27
JPH07123140B2 JPH07123140B2 (en) 1995-12-25

Family

ID=15924679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2171522A Expired - Lifetime JPH07123140B2 (en) 1990-06-28 1990-06-28 Method for manufacturing semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH07123140B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566217B1 (en) 1996-01-16 2003-05-20 Mitsubishi Denki Kabushiki Kaisha Manufacturing process for semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS502477A (en) * 1973-05-07 1975-01-11
JPS6439054A (en) * 1987-08-04 1989-02-09 Sanyo Electric Co Semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS502477A (en) * 1973-05-07 1975-01-11
JPS6439054A (en) * 1987-08-04 1989-02-09 Sanyo Electric Co Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566217B1 (en) 1996-01-16 2003-05-20 Mitsubishi Denki Kabushiki Kaisha Manufacturing process for semiconductor device

Also Published As

Publication number Publication date
JPH07123140B2 (en) 1995-12-25

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