JPS59195866A - High dielectric strength bipolar transistor - Google Patents
High dielectric strength bipolar transistorInfo
- Publication number
- JPS59195866A JPS59195866A JP7080983A JP7080983A JPS59195866A JP S59195866 A JPS59195866 A JP S59195866A JP 7080983 A JP7080983 A JP 7080983A JP 7080983 A JP7080983 A JP 7080983A JP S59195866 A JPS59195866 A JP S59195866A
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- interface
- emitter
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 7
- 229910052785 arsenic Inorganic materials 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 6
- 230000003321 amplification Effects 0.000 abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052787 antimony Inorganic materials 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 238000000926 separation method Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- -1 phosphorus ion Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
本発明は、個別部品としてのバイポーラトランジスタ、
−１ＨりＨＩＣ（Ｓ Ｓ Ｉ、 ＭＳ Ｉ、 ＬＳ
Ｉすどの集積回路）ｌこ含丑れるバイポーラトランジス
タに関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to bipolar transistors as individual components;
-1H HIC (SSI, MSI, LS
The present invention relates to bipolar transistors that can be used in integrated circuits.
従来技術
第１図５こバイポーラトランジスタの−ＩＦＩＪとして
のうｔラルＰＮＰバイポーラトランジスタを示す。Prior Art FIG. 5 shows a lateral PNP bipolar transistor as -IFIJ of the bipolar transistor.
なε、図は断面図であるがハツチングは省略にある。後
述の第３図についても同じ。Ｐ型シリコン面ｌこ、エミ
ッタ（Ｅ）、コレクタ（ｑ用のＰ十拡散頭域３．４と、
ベース（１３）コンタクト用のＮ十拡散［浜」或５が形
成されて、Ｎ−エピタキシャル層２がベースとなってい
る。コレクタ領域４Ｖｉ表面内でエミッタ領＊３を収り
囲むように形成されていてもよい。エミッタ、コレクタ
及ヒヘースコンタクトの各領域３．４及び５（こけ、そ
れぞれ表面の絶縁層（図示略）のコンタクトホールを経
て配線が施される。６は埋込層、７は分離層である。The figure is a cross-sectional view, but hatching is omitted. The same applies to Figure 3, which will be described later. P-type silicon surface 1, emitter (E), collector (P 10 diffused head area 3.4 for q,
A base (13) N-diffused [beach] 5 for the contact is formed and the N-epitaxial layer 2 is the base. It may be formed so as to enclose the emitter region *3 within the surface of the collector region 4Vi. Emitter, collector, and heat contact regions 3, 4, and 5 are connected via contact holes in the surface insulating layer (not shown). 6 is a buried layer, and 7 is a separation layer. be.
ところで、バイポーラトランジスタの重要な特性の１つ
にコレクタ・エミッタ間耐圧ＢｖｃＥｏがあるか、一般
に、この１耐圧を大きくしようとすれば素子寸法を大型
化しなくてはならないという問題がある。By the way, one of the important characteristics of a bipolar transistor is the collector-emitter breakdown voltage BvcEo, and generally speaking, if you try to increase this 1 breakdown voltage, you have to increase the element size.
１」的
本発明は、素子か大型化しないで、しかも高耐圧を有す
るバイポーラトランジスタを提供することを目的とする
ものである。The object of the present invention is to provide a bipolar transistor having a high breakdown voltage without increasing the size of the device.
バイポーラトランジスタの耐圧”ｖＣＥ、Ｊは、コレ（
″目関関１系があること、さらｔこ空乏層は高ａ度領域
（こは伸びｌこくいことか見い出された。これによれ（
ばベース饋Ｊ或の不純物濃度を高くすれば耐圧の上るこ
とが予想できるが、バイポーラトランジスタの他の重要
な特性である電流増幅率１１ ＦＥが氏上してし捷うた
め、単にベース領域の濃度を高めること１こよっては上
記目的を達成することはてきない。The withstand voltage “vCE, J” of bipolar transistor is this (
It was discovered that there is a 1-system system and that the depletion layer is in the high-a degree region.
It can be expected that by increasing the impurity concentration in the base region, the breakdown voltage will increase. The above objective cannot be achieved solely by increasing the concentration.
本発明者らは、バイポーラトランジスタの耐圧は、ラテ
ラル１−ランジスタだけでなくバーチカルトランジスタ
１こおいてもベース領域の表面の絶縁１１にとの界面付
近が重要な役占１」を果たしていることを見い出した。The present inventors have discovered that the vicinity of the interface between the base region and the insulator 11 on the surface plays an important role in the withstand voltage of a bipolar transistor, not only in the lateral transistor but also in the vertical transistor. I found it.
本発明は、この知見に基つき、その界面付近の不純物濃
度を高めることにより上記目的を達成せんとするもので
ある。Based on this knowledge, the present invention aims to achieve the above object by increasing the impurity concentration near the interface.
構１戊
本発明に、Ｐ Ｎ Ｌ）型又はＮＰＮ型のうチラルバイ
ポーラトランジスタ、又はバーチカルパイポーラトラン
ジスタにおいて、ベース領域の界面付近の不純物濃度を
ベース領域の他の部分より高濃度にしたものである。Structure 1 The present invention provides a PNL type or NPN type circular bipolar transistor or vertical bipolar transistor in which the impurity concentration near the interface of the base region is higher than that in other parts of the base region. It is.
以ド、実施例について説明する。Examples will now be described.
一実施例を第１図のｌ） Ｎ Ｐ型う？ラルトランジス
タについて示すと、ベース領域となるＮ″″″″″エピ
タキシヤル層２はシリコン酸化膜で被われているが、こ
のベース領域２の酸化膜との界面付近１０（梨子地部分
）、少なくともエミッタＩｆ￥域３とコレクタ領域４１
こ挾捷れた＠域の界面付近のＮ型不純物濃度が、そのベ
ース領域２の池の部分より高濃度番こなっている。An example is shown in Figure 1 l) NP type? Regarding the general transistor, the N″″″″″ epitaxial layer 2 serving as the base region is covered with a silicon oxide film, and at least the area 10 near the interface with the oxide film of the base region 2 (the pear-shaped part) Emitter If area 3 and collector area 41
The N-type impurity concentration near the interface of this twisted @ region is higher than that of the pond portion of the base region 2.
このベース領域の高濃度領域の厚さは、１μ肌程度以ド
、好壕しくは５０００Ａ程度である。The thickness of the high concentration region of the base region is about 1 μm thick or less, preferably about 5000 A thick.
次に、本実施例を製造工程とともに示すと、Ｐ基板１上
に砒素（ＡＳ）捷たはアンチモン（ｓｂ）を拡散キせて
埋込層６を形成した後、Ｎ 層２をエピタキシャル成長
させる。そのエピタ、キシｆｆ／し層２の全面にイオン
注入法によりリン（約１たは砒素を１〜３ Ｘ Ｉ Ｏ
／ｃａ注入する。その後、通常の工＆ｉこ従い、エピタ
キシャル層２の表面の酸化とホトエツチングを、経て、
ホウ素ＦＢ＋拡散により分離層７を形成し、イオン注入
法や拡散法により工二ツタ＠Ｍ、３． コレクタｆＲ
域４ 、 及Ｕ ヘースコシタクト領域５を形成すれば
よい。Next, to explain this embodiment together with the manufacturing process, a buried layer 6 is formed by diffusing arsenic (AS) or antimony (sb) on a P substrate 1, and then an N layer 2 is epitaxially grown. The entire surface of the epitaxial layer 2 is injected with phosphorus (approximately 1 or arsenic from 1 to 3
/ca injection. After that, the surface of the epitaxial layer 2 is oxidized and photoetched according to the usual process.
A separation layer 7 is formed by boron FB+diffusion, and Kojitsuta@M is formed by ion implantation or diffusion.3. Collector fR
Area 4, U and Height Cositact area 5 may be formed.
以上の工程により形成したうチラルｌ） Ｎ Ｐバイポ
ーラトランジスタの耐圧ＢＶＣＥＯ及び電流増幅率１１
ＦＥ と、ベース領域界面へのリンイオン（ｐ十）注
入爪との関係を第２図に示す。ただし、このデータのト
ランジスタでは、実効ベース領域寸法（エミッタ領域３
とコレクタ領域４の距離）は約６μ乳であり、エミッタ
、コレクタ両項域の深さは約２５μｍで、コレクタイ頁
域４は第１図とは異なりエミッタ頭Ｍ３を収り囲むよう
イこ形１戊されている。The breakdown voltage BVCEO and current amplification factor of the NP bipolar transistor formed by the above steps are 11
FIG. 2 shows the relationship between FE and the phosphorus ion (p+) injection nail to the base region interface. However, for the transistor with this data, the effective base area size (emitter area 3
The distance between the emitter head M3 and the collector region 4) is approximately 6 μm, the depth of both the emitter and collector regions is approximately 25 μm, and the collector region 4 is square-shaped to enclose the emitter head M3, unlike in Fig. 1. 1 has been pierced.
第２図の結果によれば、ベース領域へのイオン注入を行
なわない従来の場合（注入ｇｏの点）に比べて、イオン
注入を行なうと耐圧ＢｖＣＥＯが増大して行く。そして
、電流増幅率１１ ｐ Ｅけ減少して行くが、大きくは
イに少しない。実用上適用なイオン注入量は、第２図か
ら１〜３ Ｘ Ｉ Ｏ”／ｃｔｌ である。According to the results shown in FIG. 2, when ion implantation is performed, the withstand voltage BvCEO increases compared to the conventional case (point of implantation go) in which ion implantation into the base region is not performed. Then, the current amplification factor decreases by 11 pE, but it is not as large as A. As shown in FIG. 2, the practically applicable ion implantation amount is 1 to 3 X I O''/ctl.
この実施例のように、Ｐ Ｎ Ｐ ’）ランジスタの場
合の注入イオンとして、リンのほかに砒素を用いても同
じ結果が得られることは容易に予想される。It is easily expected that the same result will be obtained even if arsenic is used in addition to phosphorus as the implanted ions in the case of a P N P ') transistor as in this embodiment.
第３図は本発明の第２の実施例が適用されるバーチカル
ＰＮＰ トランジスタを表わす。このトランジスタで１
ｄＮ−エピタキシャル層２がベースとなることは第１図
と同じであるが、Ｐ基板ｌがコレクタとなる点で異なる
。そのため、エミッタ領域３．エピタキシャル層２（ベ
ース）、及ヒ基板１（コレクタ）の間で垂直方向のバイ
ポーラトランジスタが形成されるものであるか、コレク
タコンタクト１４が基板２１こつながる分離層７中に形
成されているため、ラテラルトランジスタと同様に水平
方向にもＰＮＰ ）、ランジスタか形成されている。そ
して、耐圧ｌこ関しては後者の水平方向のトランジスタ
成分も重要な役削を果たしている。FIG. 3 shows a vertical PNP transistor to which a second embodiment of the present invention is applied. 1 with this transistor
The dN-epitaxial layer 2 serves as the base, which is the same as in FIG. 1, but the difference is that the P substrate 1 serves as the collector. Therefore, the emitter region 3. Either a vertical bipolar transistor is formed between the epitaxial layer 2 (base) and the substrate 1 (collector), or the collector contact 14 is formed in the separation layer 7 connected to the substrate 21. Similar to the lateral transistor, a PNP (PNP) transistor is also formed in the horizontal direction. Regarding the breakdown voltage, the latter horizontal transistor component also plays an important role.
本実施列は、このようなバーチカルトランジスタｔこお
いて、第１図と同様ｌこエピタキシャル層２の全面にイ
オン注入を施し、ベースｆｆ１ｉ域の表面Ｉ浚化膜との
界面付近１０の不純物濃度を高めたものである。その結
果、ラテラルトランジスタはど顕著な効果はないとして
も、従来のトランジスタに比べると高耐圧トランジスタ
となる。In this example, in such a vertical transistor, ions are implanted into the entire surface of the epitaxial layer 2 in the same manner as in FIG. It is an enhanced version of As a result, even if the lateral transistor does not have any significant effect, it becomes a transistor with a higher breakdown voltage than the conventional transistor.
」−１，己実施例に１いずれも１°ＩＮ Ｆ トランジ
スタ（こついてのものであるが、Ｉ’Ｊ Ｐ Ｎ ）、
ランジスタ（こついても全く同様に構成することができ
る。たたし、その場合ベース領域の界面付近の制岬され
る不純物はＰ型不純物である点で相徹する。例えばエピ
タキシャル層がＰ型である場合には、その表面１こＰ型
不純物をイオン注入してその界面付近のＰ型不純物濃度
を増り口させ７′Ｌ！ばよい。”-1, in my own example 1 1° IN F transistor (I'J P N although it is a complicated one),
A transistor can be constructed in exactly the same way. However, in that case, it is consistent that the impurity to be suppressed near the interface of the base region is a P-type impurity. For example, if the epitaxial layer is P-type. In this case, it is sufficient to ion-implant a P-type impurity into the surface to increase the P-type impurity concentration near the interface by 7'L!.
また、このよう（こ表面の不純物濃度を増Ｄ■させる方
法としては、実施１１ｊの如くイオン注入法か最も適し
ているか、拡紋法ＩこよってもＯｒ能である。In addition, as a method for increasing the impurity concentration on the surface D2, the most suitable method is the ion implantation method as in Example 11j, or the spreading method I is more suitable.
さらに贅だ、バイポーラトランジスタは、エピタキシャ
ル層を部用せずに、基板半導体中に形成されることもあ
る。本発明は、そのよりな〕くイポーラトランジスタに
も適用されることは占うまでもなく、その場外、界面付
近の不純物濃１ブを増加させるためのイオン注入処理な
どは基板ｌこ施されることになる。Even more sophisticated, bipolar transistors may be formed in the substrate semiconductor without the use of epitaxial layers. Needless to say, the present invention is also applicable to supolar transistors, and ion implantation treatment to increase the impurity concentration outside the field and near the interface is performed on the substrate. It turns out.
効果
以上のように、本発明はノくイポーラトランジスタのベ
ースイ直載のその１絶λイ１模とθ）界面（＝Ｊ近の子
糸ＩＬ物濃度をベース領域の池の部分より高くしたので
、素子を大型化しないで耐圧ＢＶＣＥＯ力く増大し、し
力・も電流増幅率１１ に Ｅが大して減少しない・く
イポーラトランジスタをｆＡゴることかできた。Effects As described above, the present invention makes the concentration of IL substances near the absolute λ, 1, and θ interfaces (=J) directly mounted on the base of a polar transistor higher than that of the pond in the base region. Therefore, it was possible to greatly increase the withstand voltage BVCEO without increasing the size of the element, and to increase the current amplification factor to 11 without significantly reducing E, making it possible to convert the polar transistor to fA.
第１図１ｄ本発明の一実施例を示す（既略断面図、第２
図は同実施例による特性をイオン注入量との関・糸で示
した図、第３図は本発明の池の実施汐１ｊを示す・概略
断１１１ｉｉ図である。
１ ・基（及、２−・・エピタキシャル層（ベース）、
３ ・エミッタ領域、４・・・コレクタ頭載、１０ ・
ペースの界面付近の領域、１４・・コレクタコンタクト
。
特許出願人 株式会社リコーFig. 1d shows one embodiment of the present invention (schematic sectional view, second
The figure shows the characteristics according to the same embodiment in relation to the amount of ion implantation, and FIG. 3 is a schematic cross-sectional view 111ii showing the embodiment 1j of the pond of the present invention. 1. group (and, 2-... epitaxial layer (base),
3 ・Emitter area, 4... Collector head mounted, 10 ・
Area near the interface of the pace, 14...Collector contact. Patent applicant Ricoh Co., Ltd.
Claims (1)
領域の絶縁膜との界面伺近の不純・物濃度を高くしたこ
とを特徴とする高耐圧バイポーラトランジスタ。(1) A high-voltage bipolar transistor characterized in that the concentration of impurities and substances near the interface between the emitter region and the insulating film of the base region sandwiched between the emitter region and the collector region 1 is increased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7080983A JPS59195866A (en) | 1983-04-21 | 1983-04-21 | High dielectric strength bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7080983A JPS59195866A (en) | 1983-04-21 | 1983-04-21 | High dielectric strength bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59195866A true JPS59195866A (en) | 1984-11-07 |
Family
ID=13442262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7080983A Pending JPS59195866A (en) | 1983-04-21 | 1983-04-21 | High dielectric strength bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59195866A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61242075A (en) * | 1985-04-19 | 1986-10-28 | Sanyo Electric Co Ltd | Lateral transistor |
| JPS63219165A (en) * | 1986-10-17 | 1988-09-12 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
| JP2008211445A (en) * | 2007-02-26 | 2008-09-11 | Kyocera Mita Corp | Original feeder |
-
1983
- 1983-04-21 JP JP7080983A patent/JPS59195866A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61242075A (en) * | 1985-04-19 | 1986-10-28 | Sanyo Electric Co Ltd | Lateral transistor |
| JPS63219165A (en) * | 1986-10-17 | 1988-09-12 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
| JP2008211445A (en) * | 2007-02-26 | 2008-09-11 | Kyocera Mita Corp | Original feeder |
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