JPH06163909A - Vertical field effect transistor - Google Patents
Vertical field effect transistorInfo
- Publication number
- JPH06163909A JPH06163909A JP43A JP31702592A JPH06163909A JP H06163909 A JPH06163909 A JP H06163909A JP 43 A JP43 A JP 43A JP 31702592 A JP31702592 A JP 31702592A JP H06163909 A JPH06163909 A JP H06163909A
- Authority
- JP
- Japan
- Prior art keywords
- base region
- field effect
- effect transistor
- region
- vertical field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は縦型電界効果トランジス
タに関する。FIELD OF THE INVENTION The present invention relates to a vertical field effect transistor.
【０００２】[0002]
【従来の技術】従来の縦型電界効果トランジスタは図３
に示すように、抵抗率が０．０１Ω・ｃｍのＮ+ 型シリ
コン基板１の上に抵抗率が０．０５〜５Ω・ｃｍで厚さ
が５〜５０μｍ程度のＮ型エピタキシャル層２を形成し
た半導体基板のＮ型エピタキシャル層２の上面に拡散深
さが３〜６μｍ程度のＰ型のベース領域３を選択的に設
け、このベース領域３内に拡散深さが０．５〜２．０μ
ｍ程度のＮ+ 型のソース領域４を選択的に形成する。こ
のソース領域４の上に厚さ３０〜２００ｎｍの酸化シリ
コン膜からなるゲート酸化膜５を設け、このゲート酸化
膜５の上に、厚さ約５００ｎｍの多結晶シリコン膜から
なるゲート電極６をソース領域４に位置合せして設け、
このゲート電極６を含む表面に厚さ５００〜１０００ｎ
ｍ程度の層間絶縁膜７を堆積してパターニングしベース
領域３の一部、およびソース領域４を含む領域に開孔部
を設け、この開孔部を含む表面に厚さ１．０〜４．０μ
ｍのアルミニウム膜を被着してソース電極８を設け、シ
リコン基板１の下面にＡｕＳｂ膜からなるドレイン電極
９を形成している。2. Description of the Related Art A conventional vertical field effect transistor is shown in FIG.
As shown in FIG. 5, an N type epitaxial layer 2 having a resistivity of 0.05 to 5 Ω · cm and a thickness of about 5 to 50 μm is formed on the N + type silicon substrate 1 having a resistivity of 0.01 Ω · cm. A P-type base region 3 having a diffusion depth of about 3 to 6 μm is selectively provided on the upper surface of the N-type epitaxial layer 2 of the semiconductor substrate, and the diffusion depth within the base region 3 is 0.5 to 2.0 μ.
The N + type source region 4 of about m is selectively formed. A gate oxide film 5 made of a silicon oxide film having a thickness of 30 to 200 nm is provided on the source region 4, and a gate electrode 6 made of a polycrystalline silicon film having a thickness of about 500 nm is sourced on the gate oxide film 5. Aligned with area 4
The surface including the gate electrode 6 has a thickness of 500 to 1000 n
An interlayer insulating film 7 of about m in thickness is deposited and patterned to provide an opening in a part of the base region 3 and the region including the source region 4, and the surface including the opening has a thickness of 1.0 to 4. 0μ
A source electrode 8 is provided by depositing an aluminum film of m, and a drain electrode 9 made of an AuSb film is formed on the lower surface of the silicon substrate 1.
【０００３】[0003]
【発明が解決しようとする課題】この従来の縦型電界効
果トランジスタは、モーター等の誘導性負荷を駆動する
場合に、誘導性負荷を有する回路をターンオフしたとき
に生ずる逆起電力がソース・ドレイン間耐圧を越える
と、トランジスタは、アバランシェ降伏により、破壊に
いたる場合がある。In the conventional vertical field effect transistor, when driving an inductive load such as a motor, a counter electromotive force generated when a circuit having the inductive load is turned off is source / drain. If the breakdown voltage is exceeded, the transistor may be destroyed due to avalanche breakdown.
【０００４】図４は縦型電界効果トラジスタの等価回路
である。FIG. 4 is an equivalent circuit of a vertical field effect transistor.
【０００５】図４に示すように、図３のＮ型エピタキシ
ャル層２をコレクタ、ベース領域３をベース、ソース領
域４をエミッタとする寄生バイポーラトランジスタが縦
型電界効果トランジスタのターンオフ時に生ずる逆起電
力によりオンして電流集中し破壊に至るという問題があ
った。As shown in FIG. 4, a counter-electromotive force generated at the turn-off of a vertical field effect transistor by a parasitic bipolar transistor having the N-type epitaxial layer 2 as a collector, the base region 3 as a base, and the source region 4 as an emitter in FIG. Due to this, there was a problem that it turned on and current was concentrated, resulting in destruction.
【０００６】[0006]
【課題を解決するための手段】本発明の縦型電界効果ト
ランジスタは、一導電型半導体基板の一主面に設けた逆
導電型のベース領域と、前記ベース領域内に設けた一導
電型のソース領域と、前記ソース領域及びベース領域を
含む表面に設けたゲート絶縁膜上に設けたゲート電極と
を有する縦型電界効果トランジスタにおいて、前記ベー
ス領域が枠状に深い拡散深さを有する第１ベース領域
と、前記第１ベース領域の内周に接続して設け前記第１
ベース領域よりも高い不純物濃度を有し且つ前記第１ベ
ース領域よりも浅く形成した第２ベース領域で構成され
る。A vertical field effect transistor of the present invention comprises a base region of opposite conductivity type provided on one main surface of a semiconductor substrate of one conductivity type, and a base region of one conductivity type provided in the base region. In a vertical field effect transistor having a source region and a gate electrode provided on a gate insulating film provided on a surface including the source region and the base region, the base region has a frame-like deep diffusion depth. The base region and the inner periphery of the first base region are provided so as to be connected to each other.
The second base region has a higher impurity concentration than the base region and is formed shallower than the first base region.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００８】図１は本発明の第１の実施例を示す断面図
である。FIG. 1 is a sectional view showing a first embodiment of the present invention.
【０００９】図１に示すように、抵抗率が０．０１Ω・
ｃｍ程度のＮ+ 型シリコン基板１の上に、抵抗率が０．
０５〜２Ω・ｃｍで厚さが５〜２０μｍ程度のＮ型エピ
タキシャル層２を形成した半導体基板のＮ型エピタキシ
ャル層２の上面に拡散深さが３〜６μｍ程度の枠形のＰ
型の第１ベース領域１０を選択的に形成する。次に、第
１ベース領域１０内に拡散深さが０．５〜２．０μｍの
Ｎ+ 型のソース領域４を形成する。次に、ソース領域４
の内周に隣接し且つ第１のベース領域よりも浅い拡散深
さを有するＰ+ 型の第２ベース領域１１を形成する。以
後、従来例と同様にゲート酸化膜５を介してゲート電極
６を設け、ゲート電極６を被覆する層間絶縁膜７に開孔
部を設けてソース領域４と接続するソース電極８を設
け、シリコン基板１の下面にドレイン電極９を形成す
る。As shown in FIG. 1, the resistivity is 0.01 Ω.
A N + type silicon substrate 1 having a resistivity of about 0.
A frame-shaped P having a diffusion depth of about 3 to 6 μm on the upper surface of the N type epitaxial layer 2 of the semiconductor substrate on which the N type epitaxial layer 2 having a thickness of about 5 to 20 μm and a thickness of about 5 to 20 μm is formed.
A first base region 10 of the mold is selectively formed. Next, the N + type source region 4 having a diffusion depth of 0.5 to 2.0 μm is formed in the first base region 10. Next, the source region 4
Forming a P + -type second base region 11 adjacent to the inner periphery of the first base region and having a diffusion depth shallower than that of the first base region. Thereafter, similarly to the conventional example, the gate electrode 6 is provided through the gate oxide film 5, the inter-layer insulation film 7 covering the gate electrode 6 is provided with an opening, and the source electrode 8 connected to the source region 4 is provided. The drain electrode 9 is formed on the lower surface of the substrate 1.
【００１０】この実施例では、第１ベース領域１０は、
ゲートカットオフ電圧等を設定するため１×１０13〜２
×１０14ｃｍ-2程度のドーズ量にて不純物をイオ注入し
た後１１４０℃程度で熱処理し、所望の不純物プロファ
イルを形成する。In this embodiment, the first base region 10 is
1 × 10 13 to 2 to set the gate cutoff voltage, etc.
Impurities are ion-implanted at a dose of about × 10 14 cm -2 and then heat-treated at about 1140 ° C. to form a desired impurity profile.
【００１１】また、第２のベース領域１１は、約５×１
０15ｃｍ-2のドーズ量で第１ベース領域１０よりも浅
く、１〜３μｍ程度の拡散深さとなるようにイオン注入
して不純物プロファイルを第１ベース領域１０のそれよ
りも急峻とする。The second base region 11 has a size of about 5 × 1.
The impurity profile is made steeper than that of the first base region 10 by ion implantation so that the dose is 0 15 cm −2 , which is shallower than the first base region 10 and has a diffusion depth of about 1 to 3 μm.
【００１２】このように形成した縦型電界効果トランジ
スタのソース・ドレイン間耐圧は、第１ベース領域１０
のコーナー部にて決定されるのではなく、第２ベース領
域１１の濃度プロファイルとエピタキシャル層２の濃度
で決定される。インダクタンス成分を含む負荷をスイッ
チングするときのターンオフ時に逆起電力が発生し、こ
れがソース・ドレイン間耐圧（第２ベース領域の耐圧）
を越えるが、第２ベース領域とソース領域では寄生トラ
ンジスタが介在していないため、寄生トランジスタがオ
ンしにくくなり、破壊耐量が向上する。The withstand voltage between the source and the drain of the vertical field effect transistor thus formed has the first base region 10
It is not determined by the corner portion of the second base region 11 but by the concentration profile of the second base region 11 and the concentration of the epitaxial layer 2. A counter electromotive force is generated at turn-off when switching a load including an inductance component, and this is the withstand voltage between the source and drain (withstand voltage of the second base region).
However, since the parasitic transistor does not intervene in the second base region and the source region, it is difficult for the parasitic transistor to turn on, and the breakdown resistance is improved.
【００１３】図２は本発明の第２の実施例を示す断面図
である。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【００１４】図２に示すように、第１ベース領域１０で
囲まれた領域に第２ベース領域１１を第１ベース領域１
０よりも浅く形成した後ソース領域１０を形成した以外
は第１の実施例と同様の構成を有しており、ソース領域
４の下面に第２ベース領域１１が回り込んでいるため、
寄生トランジスタのベース抵抗が小さくでき、逆起電力
耐量が向上する。As shown in FIG. 2, the second base region 11 is provided in the region surrounded by the first base region 10.
The structure is the same as that of the first embodiment except that the source region 10 is formed after being formed shallower than 0, and the second base region 11 wraps around the lower surface of the source region 4.
The base resistance of the parasitic transistor can be reduced and the back electromotive force withstand capability is improved.
【００１５】[0015]
【発明の効果】以上説明したように本発明は、枠形に設
けた第１のベース領域の内側に第１のベース領域よりも
高い不純物濃度の第２のベース領域を第１のベース領域
よりも浅く形成することにより、インダクタンス成分を
含む負荷のスイッチング時の逆起電力耐量を向上できる
という効果を有する。As described above, according to the present invention, the second base region having an impurity concentration higher than that of the first base region is provided inside the first base region provided in the frame shape. Forming it also shallower has the effect of improving the back electromotive force withstand level when switching a load including an inductance component.
【図１】本発明の第１の実施例を示す断面図。FIG. 1 is a sectional view showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す断面図。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【図３】従来の縦型電界効果トランジスタの一例を示す
断面図。FIG. 3 is a cross-sectional view showing an example of a conventional vertical field effect transistor.
１ Ｎ+ 型シリコン基板 ２ Ｎ型エピタキシャル層 ３ ベース領域 ４ ソース領域 ５ ゲート酸化膜 ６ ゲート電極 ７ 層間絶縁膜 ８ ソース電極 ９ ドレイン電極 １０ 第１ベース領域 １１ 第２ベース領域1 N + type silicon substrate 2 N type epitaxial layer 3 base region 4 source region 5 gate oxide film 6 gate electrode 7 interlayer insulating film 8 source electrode 9 drain electrode 10 first base region 11 second base region
Claims (1)
導電型のベース領域と、前記ベース領域内に設けた一導
電型のソース領域と、前記ソース領域及びベース領域を
含む表面に設けたゲート絶縁膜上に設けたゲート電極と
を有する縦型電界効果トランジスタにおいて、前記ベー
ス領域が枠状に深い拡散深さを有する第１ベース領域
と、前記第１ベース領域の内周に接続して設け前記第１
ベース領域よりも高い不純物濃度を有し且つ前記第１ベ
ース領域よりも浅く形成した第２ベース領域で構成され
ることを特徴とする縦型電界効果トランジスタ。1. A base region of opposite conductivity type provided on one main surface of a semiconductor substrate of one conductivity type, a source region of one conductivity type provided in the base region, and a surface including the source region and the base region. In a vertical field effect transistor having a gate electrode provided on a provided gate insulating film, the base region is connected to a first base region having a frame-like deep diffusion depth and an inner circumference of the first base region. Provided as the first
A vertical field effect transistor, comprising a second base region which has an impurity concentration higher than that of the base region and is formed shallower than the first base region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43A JPH06163909A (en) | 1992-11-26 | 1992-11-26 | Vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43A JPH06163909A (en) | 1992-11-26 | 1992-11-26 | Vertical field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06163909A true JPH06163909A (en) | 1994-06-10 |
Family
ID=18083587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP43A Pending JPH06163909A (en) | 1992-11-26 | 1992-11-26 | Vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06163909A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08204175A (en) * | 1995-01-30 | 1996-08-09 | Nec Yamagata Ltd | Vertical mos transistor |
| WO1997016853A1 (en) * | 1995-11-02 | 1997-05-09 | National Semiconductor Corporation | Insulated gate semiconductor devices with implants for improved ruggedness |
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
| US5973361A (en) * | 1996-03-06 | 1999-10-26 | Magepower Semiconductor Corporation | DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness |
-
1992
- 1992-11-26 JP JP43A patent/JPH06163909A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
| US5897355A (en) * | 1994-08-03 | 1999-04-27 | National Semiconductor Corporation | Method of manufacturing insulated gate semiconductor device to improve ruggedness |
| JPH08204175A (en) * | 1995-01-30 | 1996-08-09 | Nec Yamagata Ltd | Vertical mos transistor |
| WO1997016853A1 (en) * | 1995-11-02 | 1997-05-09 | National Semiconductor Corporation | Insulated gate semiconductor devices with implants for improved ruggedness |
| KR100360079B1 (en) * | 1995-11-02 | 2003-03-15 | 내셔널 세미콘덕터 코포레이션 | Manufacturing method of insulated gate semiconductor device to improve robustness |
| US5973361A (en) * | 1996-03-06 | 1999-10-26 | Magepower Semiconductor Corporation | DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness |
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