JPS6433967A - Input mechanism of charge transfer device - Google Patents

Input mechanism of charge transfer device

Info

Publication number
JPS6433967A
JPS6433967A JP18873387A JP18873387A JPS6433967A JP S6433967 A JPS6433967 A JP S6433967A JP 18873387 A JP18873387 A JP 18873387A JP 18873387 A JP18873387 A JP 18873387A JP S6433967 A JPS6433967 A JP S6433967A
Authority
JP
Japan
Prior art keywords
voltage
input signal
potential barrier
signal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18873387A
Other languages
Japanese (ja)
Inventor
Nozomi Ozaki
Takashi Mitsuida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP18873387A priority Critical patent/JPS6433967A/en
Publication of JPS6433967A publication Critical patent/JPS6433967A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a device in which effects of a parasitic capacity can be eliminated to improve linearity and a structure is simple to be realized easily, by providing a specific signal holding means, a source diffusion, a first and second gate electrodes, and control means respectively. CONSTITUTION:Here provided a signal holding means including a capacitor element Co, a source diffusion (SD) 1 to which an input signal Vin held in the capacitor element Co is supplied and which sets a Fermi level corresponding to the voltage of the input signal Vin, a first gate electrode 3 which produces a potential barrier adjacent to the SD1 according to the voltage of a first control signal IG1, and a second gate electrode 4 which produces a potential well with predetermined depth adjacent to the potential barrier according to the voltage of a second control signal IG2. Moreover, a control means is provided which so controls the first and second control signals IG1, IG2 as to inject the signal charges corresponding to the difference between the Fermi level of the SD1 corresponding to the voltage of the input signal Vin and the level of the potential barrier into the potential well.
JP18873387A 1987-07-30 1987-07-30 Input mechanism of charge transfer device Pending JPS6433967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18873387A JPS6433967A (en) 1987-07-30 1987-07-30 Input mechanism of charge transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18873387A JPS6433967A (en) 1987-07-30 1987-07-30 Input mechanism of charge transfer device

Publications (1)

Publication Number Publication Date
JPS6433967A true JPS6433967A (en) 1989-02-03

Family

ID=16228822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18873387A Pending JPS6433967A (en) 1987-07-30 1987-07-30 Input mechanism of charge transfer device

Country Status (1)

Country Link
JP (1) JPS6433967A (en)

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