JPS643060B2 - - Google Patents

Info

Publication number
JPS643060B2
JPS643060B2 JP9780181A JP9780181A JPS643060B2 JP S643060 B2 JPS643060 B2 JP S643060B2 JP 9780181 A JP9780181 A JP 9780181A JP 9780181 A JP9780181 A JP 9780181A JP S643060 B2 JPS643060 B2 JP S643060B2
Authority
JP
Japan
Prior art keywords
package
seal pattern
bonding pad
pattern
inner layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9780181A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57211754A (en
Inventor
Masahiro Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9780181A priority Critical patent/JPS57211754A/ja
Publication of JPS57211754A publication Critical patent/JPS57211754A/ja
Publication of JPS643060B2 publication Critical patent/JPS643060B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP9780181A 1981-06-24 1981-06-24 Package Granted JPS57211754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9780181A JPS57211754A (en) 1981-06-24 1981-06-24 Package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9780181A JPS57211754A (en) 1981-06-24 1981-06-24 Package

Publications (2)

Publication Number Publication Date
JPS57211754A JPS57211754A (en) 1982-12-25
JPS643060B2 true JPS643060B2 (enrdf_load_stackoverflow) 1989-01-19

Family

ID=14201878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9780181A Granted JPS57211754A (en) 1981-06-24 1981-06-24 Package

Country Status (1)

Country Link
JP (1) JPS57211754A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5910240A (ja) * 1982-07-09 1984-01-19 Nec Corp 半導体装置
JPS5972749A (ja) * 1982-10-19 1984-04-24 Nec Corp 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5336468A (en) * 1976-09-17 1978-04-04 Hitachi Ltd Package for integrated circuit
JPS5487512A (en) * 1977-12-24 1979-07-12 Sony Corp Cassette type vtr

Also Published As

Publication number Publication date
JPS57211754A (en) 1982-12-25

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