JPS6429023A - Signal converter - Google Patents

Signal converter

Info

Publication number
JPS6429023A
JPS6429023A JP18509387A JP18509387A JPS6429023A JP S6429023 A JPS6429023 A JP S6429023A JP 18509387 A JP18509387 A JP 18509387A JP 18509387 A JP18509387 A JP 18509387A JP S6429023 A JPS6429023 A JP S6429023A
Authority
JP
Japan
Prior art keywords
circuit
fault
signal
output
signal conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18509387A
Other languages
Japanese (ja)
Inventor
Kazuo Hagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18509387A priority Critical patent/JPS6429023A/en
Publication of JPS6429023A publication Critical patent/JPS6429023A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To detect a fault, and at the same time, to protect an output signal at the time of the fault by assigning one input signal simultaneously to two signal conversion circuits, and comparing the outputs of them. CONSTITUTION:N-number of the input signals 1 are assigned to N-number of signal conversion circuits 8 respectively by an input control circuit 7, and at the same time, the same input signal as the input signal, assigned to the signal conversion circuit 8 to detect the fault, is assigned to the N+1-th signal conversion circuit 8. Here, two outputs from an output selecting circuit 10 are compared by a comparing circuit 11, and a result is outputted to a control circuit 13. Then, time since the assignment of the input signal is changed until the internal state of the signal conversion circuit 8 settles is measured by a timer circuit 12, and afterwards, the output of the comparison circuit 11 is checked by the control circuit 13, and the fault is detected. At the same time, from the result, by changing the output of the signal conversion circuit 8, in which the fault exists, to the output of the normal signal conversion circuit 8, the output signal 2 at the time of the fault is protected.
JP18509387A 1987-07-23 1987-07-23 Signal converter Pending JPS6429023A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18509387A JPS6429023A (en) 1987-07-23 1987-07-23 Signal converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18509387A JPS6429023A (en) 1987-07-23 1987-07-23 Signal converter

Publications (1)

Publication Number Publication Date
JPS6429023A true JPS6429023A (en) 1989-01-31

Family

ID=16164719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18509387A Pending JPS6429023A (en) 1987-07-23 1987-07-23 Signal converter

Country Status (1)

Country Link
JP (1) JPS6429023A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08122413A (en) * 1994-10-28 1996-05-17 Nec Corp Semiconductor integrated circuit and test method therefor
JP2011176438A (en) * 2010-02-23 2011-09-08 Toshiba Mitsubishi-Electric Industrial System Corp A/d conversion device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08122413A (en) * 1994-10-28 1996-05-17 Nec Corp Semiconductor integrated circuit and test method therefor
JP2011176438A (en) * 2010-02-23 2011-09-08 Toshiba Mitsubishi-Electric Industrial System Corp A/d conversion device

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