JPS6427724U - - Google Patents
Info
- Publication number
- JPS6427724U JPS6427724U JP12341587U JP12341587U JPS6427724U JP S6427724 U JPS6427724 U JP S6427724U JP 12341587 U JP12341587 U JP 12341587U JP 12341587 U JP12341587 U JP 12341587U JP S6427724 U JPS6427724 U JP S6427724U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- clk
- subtraction
- control circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12341587U JPS6427724U (de) | 1987-08-11 | 1987-08-11 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12341587U JPS6427724U (de) | 1987-08-11 | 1987-08-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6427724U true JPS6427724U (de) | 1989-02-17 |
Family
ID=31372247
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12341587U Pending JPS6427724U (de) | 1987-08-11 | 1987-08-11 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6427724U (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02124060U (de) * | 1989-03-27 | 1990-10-12 |
-
1987
- 1987-08-11 JP JP12341587U patent/JPS6427724U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02124060U (de) * | 1989-03-27 | 1990-10-12 |
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