JPS6427093A - Decoder circuit - Google Patents

Decoder circuit

Info

Publication number
JPS6427093A
JPS6427093A JP62184465A JP18446587A JPS6427093A JP S6427093 A JPS6427093 A JP S6427093A JP 62184465 A JP62184465 A JP 62184465A JP 18446587 A JP18446587 A JP 18446587A JP S6427093 A JPS6427093 A JP S6427093A
Authority
JP
Japan
Prior art keywords
decoder
circuit
output
base
amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62184465A
Other languages
Japanese (ja)
Other versions
JP2600695B2 (en
Inventor
Yoji Idei
Noriyuki Honma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62184465A priority Critical patent/JP2600695B2/en
Publication of JPS6427093A publication Critical patent/JPS6427093A/en
Application granted granted Critical
Publication of JP2600695B2 publication Critical patent/JP2600695B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To reduce the amplitude of a decoder line, to simultaneously decrease the time constant of output leading edge and to speed-up the action of a decoder circuit by providing a circuit to impress a signal generating circuit in proportion to a decoder output signal and a circuit to level-shift the output and to impress the output to the base, etc., of a transistor, etc. CONSTITUTION:A load resistance RD is divided into two, RD1 and RD2, and a dividing point is connected through a level shifting circuit consisting of an emitter and a constant current source to the base of a decoder transistor TRQD. This level shifting circuit reduces the base potential lower than the potential of the dividing point of the resistance for the line amplitude, decreases an output leading time constant, thereby acting to keep lower for an inter-base-emitter voltage VBE of an emitter follower QE. For this reason, at whatever point division ratio of the load resistance may be set, the decoder TRQD is not saturated, and can decrease the signal amplitude of the decoder line to the minimum value required for the action.
JP62184465A 1987-07-23 1987-07-23 Decoder circuit Expired - Lifetime JP2600695B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62184465A JP2600695B2 (en) 1987-07-23 1987-07-23 Decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62184465A JP2600695B2 (en) 1987-07-23 1987-07-23 Decoder circuit

Publications (2)

Publication Number Publication Date
JPS6427093A true JPS6427093A (en) 1989-01-30
JP2600695B2 JP2600695B2 (en) 1997-04-16

Family

ID=16153629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62184465A Expired - Lifetime JP2600695B2 (en) 1987-07-23 1987-07-23 Decoder circuit

Country Status (1)

Country Link
JP (1) JP2600695B2 (en)

Also Published As

Publication number Publication date
JP2600695B2 (en) 1997-04-16

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