JPS5521624A - Read-in circuit for fluctuating signal - Google Patents
Read-in circuit for fluctuating signalInfo
- Publication number
- JPS5521624A JPS5521624A JP9438278A JP9438278A JPS5521624A JP S5521624 A JPS5521624 A JP S5521624A JP 9438278 A JP9438278 A JP 9438278A JP 9438278 A JP9438278 A JP 9438278A JP S5521624 A JPS5521624 A JP S5521624A
- Authority
- JP
- Japan
- Prior art keywords
- output
- fed
- comparator
- input
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/02—Input circuits
- H03K21/023—Input circuits comprising pulse shaping or differentiating circuits
Landscapes
- Geophysics And Detection Of Objects (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To accurately count the number of times of fluctuation of signal, by feeding the input signal to the integration circuit with reversed conduction and by the level comparison of the difference between the output of the integration circuit and the input signal. CONSTITUTION:The fluctuated signal input is fed to (-) of the differential amplifier 1 and also to the selection circuits 2 and 3. The output of the differential amplifier 1 is fed to (-) of the comparator 4 and the output is fed to the two drivers 6 and 7. When the output of the comparator 4 is (+), the driver 7 is ON and the driver 6 is OFF, and when the output of the comparator 4 is (-), 7 is OFF and 6 is ON. In the selection circuits 2 and 3, the diodes 8 and 9 are inserted in reverse connection for conduction, and they are ON when the drivers are ON. The output of the selection circuits is fed to the integration circuit 10 as the (+) input of the differential amplifier 1. As the (+) input of the comparator 4, the comparator set value added with the hysteresis of output is fed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53094382A JPS6019855B2 (en) | 1978-08-02 | 1978-08-02 | Counting circuit for undulating input signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53094382A JPS6019855B2 (en) | 1978-08-02 | 1978-08-02 | Counting circuit for undulating input signals |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5521624A true JPS5521624A (en) | 1980-02-15 |
JPS6019855B2 JPS6019855B2 (en) | 1985-05-18 |
Family
ID=14108748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53094382A Expired JPS6019855B2 (en) | 1978-08-02 | 1978-08-02 | Counting circuit for undulating input signals |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6019855B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0687065A2 (en) * | 1994-06-06 | 1995-12-13 | Ramtron International Corporation | Noise and glitch suppressing filter with feedback |
-
1978
- 1978-08-02 JP JP53094382A patent/JPS6019855B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0687065A2 (en) * | 1994-06-06 | 1995-12-13 | Ramtron International Corporation | Noise and glitch suppressing filter with feedback |
EP0687065A3 (en) * | 1994-06-06 | 1996-12-11 | Ramtron Int Corp | Noise and glitch suppressing filter with feedback |
Also Published As
Publication number | Publication date |
---|---|
JPS6019855B2 (en) | 1985-05-18 |
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