JPS5527714A - Duty cycle control circuit - Google Patents

Duty cycle control circuit

Info

Publication number
JPS5527714A
JPS5527714A JP10041678A JP10041678A JPS5527714A JP S5527714 A JPS5527714 A JP S5527714A JP 10041678 A JP10041678 A JP 10041678A JP 10041678 A JP10041678 A JP 10041678A JP S5527714 A JPS5527714 A JP S5527714A
Authority
JP
Japan
Prior art keywords
signal
duty cycle
amplifier
bias
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10041678A
Other languages
Japanese (ja)
Inventor
Tetsuya Iida
Kenro Sakagami
Yasoji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10041678A priority Critical patent/JPS5527714A/en
Publication of JPS5527714A publication Critical patent/JPS5527714A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses

Abstract

PURPOSE:To secure an automatic control for the duty cyle of the output pulse signal by making use of the voltage of the DC level according to the duty cycle of the output pulse signal to the DC bias of the amplifier circuit of the input AC signal. CONSTITUTION:The AC signal Sphi is supplied to reverse amplifier I1 via coupled capacity 15. The DC bias is supplied to amplifier I1 from duty cycle detection part 1 via resistancd 14. Based on this bias, Sphi receives the waveform shaping and amplification and accordingly varies in accordance with the duty cycle of the output pulse of amplifier I1. After this, reverse amplifier I2 gives the waveform shaping and amplification to I1 output, and the output is applied to pulse generation circuit 16 to be changed into pulse signal phi0 and then applied to the gate of MOSFET4 of part 1. FET4 is turned on and off by the high or low level of signal phi0. As a sresult, the DC bias is obtained through filter F and in accordance with the duty cycle of signal phi0 to be applied to input signal Sphi.
JP10041678A 1978-08-17 1978-08-17 Duty cycle control circuit Pending JPS5527714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10041678A JPS5527714A (en) 1978-08-17 1978-08-17 Duty cycle control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10041678A JPS5527714A (en) 1978-08-17 1978-08-17 Duty cycle control circuit

Publications (1)

Publication Number Publication Date
JPS5527714A true JPS5527714A (en) 1980-02-28

Family

ID=14273370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10041678A Pending JPS5527714A (en) 1978-08-17 1978-08-17 Duty cycle control circuit

Country Status (1)

Country Link
JP (1) JPS5527714A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181140U (en) * 1981-05-14 1982-11-17
JPS586434U (en) * 1981-07-02 1983-01-17 アイワ株式会社 Waveform shaping circuit
JPS59172820A (en) * 1983-03-22 1984-09-29 Fujitsu Ltd Limiter amplifier
CN103988430A (en) * 2011-10-13 2014-08-13 三菱日立电力系统株式会社 Pulse generation device and pulse generation method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS508454A (en) * 1973-05-21 1975-01-28

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS508454A (en) * 1973-05-21 1975-01-28

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57181140U (en) * 1981-05-14 1982-11-17
JPS586434U (en) * 1981-07-02 1983-01-17 アイワ株式会社 Waveform shaping circuit
JPH0119470Y2 (en) * 1981-07-02 1989-06-06
JPS59172820A (en) * 1983-03-22 1984-09-29 Fujitsu Ltd Limiter amplifier
CN103988430A (en) * 2011-10-13 2014-08-13 三菱日立电力系统株式会社 Pulse generation device and pulse generation method
CN103988430B (en) * 2011-10-13 2016-08-17 三菱日立电力系统株式会社 Pulse generating unit and pulse generating method

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