JPS6424507A - Two-phase clock generating circuit - Google Patents

Abstract

PURPOSE:To obtain a high-accuracy, two-phase clock generating circuit which is not affected by variations of various parameters by detecting the interval time of a two-phase clock, and feeding the detected value back negatively and controlling the delay quantity of a delay circuit. CONSTITUTION:A converting circuit 14 converts a single-phase clock into the two-phase clock and incorporates voltage-controlled delay circuit 1d and 2d whose delay quantities can be controlled with a control voltage. An OR circuit 15 detects the active state of the two-phase clock outputted to terminals 12 and 13. Then current sources 16 and 17 charge a capacitor 19 and either one turns on through the operation of an inverting circuit 18 according to the output state of the OR circuit 15. The terminal voltage across the capacitor 19 is fed back to the voltage-controlled delay circuits 1d and 2d to form a negative feedback loop. The interval time of the two-phase clock is detected and fed back negatively to control the delay quantities of the delay circuits, thus obtaining the two-phase clock generating circuit which is not affected by variations of various parameters.