JPS642439U - - Google Patents
Info
- Publication number
- JPS642439U JPS642439U JP1987095796U JP9579687U JPS642439U JP S642439 U JPS642439 U JP S642439U JP 1987095796 U JP1987095796 U JP 1987095796U JP 9579687 U JP9579687 U JP 9579687U JP S642439 U JPS642439 U JP S642439U
- Authority
- JP
- Japan
- Prior art keywords
- pressing
- view
- lead
- sectional
- positioning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000037431 insertion Effects 0.000 claims description 2
- 238000003780 insertion Methods 0.000 claims description 2
- 239000000725 suspension Substances 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
第1図はこの考案の一実施例を示す断面図、第
2図はその−線における断面図、第3図はそ
の要部平面図、第4図はその要部断面図、第5図
はこの考案の他の実施例を示す断面図、第6図は
その部分断面平面図、第7図は従来装置の断面図
、第8図はその部分平面図、第9図はその部分断
面図、第10図はその要部断面図、第11図は要
部平面断面図である。 図中、2はつりリード、6はダイパツド、12
はインナリード、13は挿入溝、14はダイパツ
ド位置決め溝、40はフレーム押え、40aはつ
りリード押え部、50はヒートブロツクである。
なお、各図中同一符号は同一又は相当部分を示す
。
2図はその−線における断面図、第3図はそ
の要部平面図、第4図はその要部断面図、第5図
はこの考案の他の実施例を示す断面図、第6図は
その部分断面平面図、第7図は従来装置の断面図
、第8図はその部分平面図、第9図はその部分断
面図、第10図はその要部断面図、第11図は要
部平面断面図である。 図中、2はつりリード、6はダイパツド、12
はインナリード、13は挿入溝、14はダイパツ
ド位置決め溝、40はフレーム押え、40aはつ
りリード押え部、50はヒートブロツクである。
なお、各図中同一符号は同一又は相当部分を示す
。
Claims (1)
- ダイパツトを位置決めする位置決め面と、この
第2の平面よりも深く形成され、つりリードを挿
入し得る挿入溝とを有するブロツク、及びインナ
ーリードを押圧する第1の押圧部と上記挿入溝内
で上記つりリードを押圧する第2の押圧部とを有
する押え部材を備えたボンデイング装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987095796U JPS642439U (ja) | 1987-06-22 | 1987-06-22 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987095796U JPS642439U (ja) | 1987-06-22 | 1987-06-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS642439U true JPS642439U (ja) | 1989-01-09 |
Family
ID=31320513
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987095796U Pending JPS642439U (ja) | 1987-06-22 | 1987-06-22 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS642439U (ja) |
-
1987
- 1987-06-22 JP JP1987095796U patent/JPS642439U/ja active Pending
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