JPH0474462U - - Google Patents
Info
- Publication number
- JPH0474462U JPH0474462U JP11817790U JP11817790U JPH0474462U JP H0474462 U JPH0474462 U JP H0474462U JP 11817790 U JP11817790 U JP 11817790U JP 11817790 U JP11817790 U JP 11817790U JP H0474462 U JPH0474462 U JP H0474462U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- die pad
- solder
- utility
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例であるＩＣフレー
ムにＩＣチツプをはんだ付けした状態を示す斜視
図、第２図は第１図の−線における断面図、
第３図は従来のＩＣフレームにＩＣチツプをはん
だ付けした状態を示す斜視図、第４図は第３図の
−線における断面図である。 図において、１はダイパツド、１ａはダイパツ
ド吊り、１ｂはダイパツド１の内実際ＩＣチツプ
が載るくぼみを設けた部分、１ｃはダイパツド１
の内の周辺部分、２はＩＣチツプ、３ははんだ、
３ａははんだ不足部分、３ｂははんだ過剰部分を
示す。なお、図中、同一符号は同一、または相当
部分を示す。
ムにＩＣチツプをはんだ付けした状態を示す斜視
図、第２図は第１図の−線における断面図、
第３図は従来のＩＣフレームにＩＣチツプをはん
だ付けした状態を示す斜視図、第４図は第３図の
−線における断面図である。 図において、１はダイパツド、１ａはダイパツ
ド吊り、１ｂはダイパツド１の内実際ＩＣチツプ
が載るくぼみを設けた部分、１ｃはダイパツド１
の内の周辺部分、２はＩＣチツプ、３ははんだ、
３ａははんだ不足部分、３ｂははんだ過剰部分を
示す。なお、図中、同一符号は同一、または相当
部分を示す。
Claims (1)
- ＩＣフレームにおいてダイパツド部のＩＣチツ
プが載る部分を、そのまわり部分より低くしては
んだ溜りを設けたことを特徴とするＩＣフレーム
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11817790U JPH0474462U (ja) | 1990-11-09 | 1990-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11817790U JPH0474462U (ja) | 1990-11-09 | 1990-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0474462U true JPH0474462U (ja) | 1992-06-30 |
Family
ID=31866081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11817790U Pending JPH0474462U (ja) | 1990-11-09 | 1990-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0474462U (ja) |
-
1990
- 1990-11-09 JP JP11817790U patent/JPH0474462U/ja active Pending