JPS642341A - Package for integrated circuit - Google Patents

Package for integrated circuit

Info

Publication number
JPS642341A
JPS642341A JP15718587A JP15718587A JPS642341A JP S642341 A JPS642341 A JP S642341A JP 15718587 A JP15718587 A JP 15718587A JP 15718587 A JP15718587 A JP 15718587A JP S642341 A JPS642341 A JP S642341A
Authority
JP
Japan
Prior art keywords
integrated circuit
package
main body
pins
side surfaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15718587A
Other languages
Japanese (ja)
Other versions
JPH012341A (en
Inventor
Katsuji Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15718587A priority Critical patent/JPS642341A/en
Publication of JPH012341A publication Critical patent/JPH012341A/en
Publication of JPS642341A publication Critical patent/JPS642341A/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To contrive the improvement of the packaging efficiency of the title package to a printed board by a method wherein a plurality of lead pins, which are connected with the lead terminals of an integrated circuit, are provided in such a way as to protrude on the bottom surface and the side surfaces of the external surface of a package main body.
CONSTITUTION: A package for an integrated circuit is provided with a package main body 1 and lead pins 2 and 3 provided on the bottom surface and the side surfaces of the main body 1. The main body 1 is formed of an insulating material in a box type, the side surfaces 5 are formed into a rectangle, the bottom surface 4 is formed into an almost square and the main body 1 is formed into a thin type as a whole. The integrated circuit is housed in the interior of the main body 1 and lead terminals of the integrated circuit are connected to the lead pins 2 and 3. The pins 2 are inserted in through holes of a printed board and the pins 3 are connected or soldered to external terminals. In such a way, the packaging efficiency of the package for the integrated circuit to the printed board can be increased.
COPYRIGHT: (C)1989,JPO&Japio
JP15718587A 1987-06-24 1987-06-24 Package for integrated circuit Pending JPS642341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15718587A JPS642341A (en) 1987-06-24 1987-06-24 Package for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15718587A JPS642341A (en) 1987-06-24 1987-06-24 Package for integrated circuit

Publications (2)

Publication Number Publication Date
JPH012341A JPH012341A (en) 1989-01-06
JPS642341A true JPS642341A (en) 1989-01-06

Family

ID=15644053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15718587A Pending JPS642341A (en) 1987-06-24 1987-06-24 Package for integrated circuit

Country Status (1)

Country Link
JP (1) JPS642341A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02268647A (en) * 1989-04-10 1990-11-02 Nippon Flour Mills Co Ltd Method for making cake and surface improving agent for cake

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02268647A (en) * 1989-04-10 1990-11-02 Nippon Flour Mills Co Ltd Method for making cake and surface improving agent for cake

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