JPS6419997U - - Google Patents
Info
- Publication number
- JPS6419997U JPS6419997U JP11383287U JP11383287U JPS6419997U JP S6419997 U JPS6419997 U JP S6419997U JP 11383287 U JP11383287 U JP 11383287U JP 11383287 U JP11383287 U JP 11383287U JP S6419997 U JPS6419997 U JP S6419997U
- Authority
- JP
- Japan
- Prior art keywords
- electronic device
- main body
- dma controller
- display
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図は本考案の１実施例を示すブロツク図で
あり、第２図は本考案の他の実施例を示すブロツ
ク図である。
図中の符号、１……複写機本体のマイクロプロ
セツサ（ＣＰＵ）、２……ＲＯＭ、３……ＲＡＭ
、４……ＤＭＡコントローラ、５……ドライバー
・レシーバ、６……内部バス、７……制御部、８
……表示出力部、９……スイツチ入力部、１０…
…接続ケーブル、１１……高集積ＣＰＵ。
FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. Symbols in the diagram: 1...Microprocessor (CPU) of the copying machine body, 2...ROM, 3...RAM
, 4...DMA controller, 5...driver/receiver, 6...internal bus, 7...control unit, 8
...Display output section, 9...Switch input section, 10...
...Connection cable, 11...Highly integrated CPU.
Claims (1)
なる電子機器において、該機器本体のメモリと、
コントロールパネル部および表示部との間を接続
ケーブルにより接続するとともに、両装置間のデ
ータ転送を、ＤＭＡコントローラによつて行うこ
とを特徴とする操作・表示装置を有する電子機器
。 (2) 前記ＤＭＡコントローラが前記電子機器本
体に設けられていることを特徴とする実用新案登
録請求の範囲第１項記載の操作・表示装置を有す
る電子機器。 (3) 前記ＤＭＡコントローラが、電子機器本体
のマイクロプロセツサに内蔵されていることを特
徴とする実用新案登録請求の範囲第１項または第
２項に記載の操作・表示装置を有する電子機器。[Claims for Utility Model Registration] (1) In an electronic device that is provided with a control panel section and a display section, the memory of the main body of the device,
An electronic device having an operation/display device, characterized in that a control panel section and a display section are connected by a connection cable, and data transfer between the two devices is performed by a DMA controller. (2) An electronic device having an operation/display device according to claim 1, wherein the DMA controller is provided in the main body of the electronic device. (3) An electronic device having an operation/display device according to claim 1 or 2, wherein the DMA controller is built into a microprocessor of the main body of the electronic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11383287U JPS6419997U (en) | 1987-07-27 | 1987-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11383287U JPS6419997U (en) | 1987-07-27 | 1987-07-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6419997U true JPS6419997U (en) | 1989-01-31 |
Family
ID=31354023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11383287U Pending JPS6419997U (en) | 1987-07-27 | 1987-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6419997U (en) |
-
1987
- 1987-07-27 JP JP11383287U patent/JPS6419997U/ja active Pending
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