JPS6418854A - Address converting circuit for picture memory - Google Patents

Address converting circuit for picture memory

Info

Publication number
JPS6418854A
JPS6418854A JP17635487A JP17635487A JPS6418854A JP S6418854 A JPS6418854 A JP S6418854A JP 17635487 A JP17635487 A JP 17635487A JP 17635487 A JP17635487 A JP 17635487A JP S6418854 A JPS6418854 A JP S6418854A
Authority
JP
Japan
Prior art keywords
memory
signal
bits
address
inverted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17635487A
Other languages
Japanese (ja)
Inventor
Kenichi Matsumura
Kenji Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17635487A priority Critical patent/JPS6418854A/en
Publication of JPS6418854A publication Critical patent/JPS6418854A/en
Pending legal-status Critical Current

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  • Image Input (AREA)

Abstract

PURPOSE:To ensure the highly efficient address conversion by using a picture memory which is divided into four types of memory groups and a gate which is controlled by an address switch signal. CONSTITUTION:When an address switch signal 5 is set at 'H', the gates related to the inversion are all closed and therefore the operation is carried out in an exactly same way as that of an ordinary memory access. When the signal 5 is set at 'L', the lower level 9 bits 6 and the higher 9 bits 7 out of the lower level 18 bits of an address signal are inverted. Furthermore the data buses of the output destinations of the memory data are set opposite to each other between a memory group A and a memory group B. At the same time, an enable signal 8 and an upper enable signal 9 supplied to an input terminal CS of each of the memory groups 10A-10D are switched with each other. Thus the free accesses are possible for each byte or word even in an inverted memory addressing state.
JP17635487A 1987-07-14 1987-07-14 Address converting circuit for picture memory Pending JPS6418854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17635487A JPS6418854A (en) 1987-07-14 1987-07-14 Address converting circuit for picture memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17635487A JPS6418854A (en) 1987-07-14 1987-07-14 Address converting circuit for picture memory

Publications (1)

Publication Number Publication Date
JPS6418854A true JPS6418854A (en) 1989-01-23

Family

ID=16012139

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17635487A Pending JPS6418854A (en) 1987-07-14 1987-07-14 Address converting circuit for picture memory

Country Status (1)

Country Link
JP (1) JPS6418854A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006099447A (en) * 2004-09-29 2006-04-13 Sony Corp Memory mapping method and memory interface circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853073A (en) * 1981-09-24 1983-03-29 Hitachi Ltd Address designation controller in memory
JPS61173354A (en) * 1985-01-29 1986-08-05 Usac Electronics Ind Co Ltd Image memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853073A (en) * 1981-09-24 1983-03-29 Hitachi Ltd Address designation controller in memory
JPS61173354A (en) * 1985-01-29 1986-08-05 Usac Electronics Ind Co Ltd Image memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006099447A (en) * 2004-09-29 2006-04-13 Sony Corp Memory mapping method and memory interface circuit

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