JPS5616254A - Data write-in and readout system for microcomputer - Google Patents

Data write-in and readout system for microcomputer

Info

Publication number
JPS5616254A
JPS5616254A JP9136479A JP9136479A JPS5616254A JP S5616254 A JPS5616254 A JP S5616254A JP 9136479 A JP9136479 A JP 9136479A JP 9136479 A JP9136479 A JP 9136479A JP S5616254 A JPS5616254 A JP S5616254A
Authority
JP
Japan
Prior art keywords
address
bit
data
ram1w4
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9136479A
Other languages
Japanese (ja)
Other versions
JPS5939830B2 (en
Inventor
Norihiko Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universal KK
Original Assignee
Universal KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universal KK filed Critical Universal KK
Priority to JP54091364A priority Critical patent/JPS5939830B2/en
Publication of JPS5616254A publication Critical patent/JPS5616254A/en
Publication of JPS5939830B2 publication Critical patent/JPS5939830B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the number of RAMs, by using RAM at page mode, sequentially writing in the data of one word with split at write-in, and taking one word through the synthesis of the data sequentially read out at readout.
CONSTITUTION: The microcomputer of bit system N is taken as the 8-bit system and RAM1W4 of 16K-word×1-bit are used to constitute the screen RAM of TV game machine. The RAM1W4 are provided with the address input terminal in 7- bit, CPU address signal and TV scanning signal are output with switching with the CPU/TV switching signal at the address selector 5 for output, the address signal switches the row address and column address, and the page address, and RAM1W4 are accessed by the row address in 7-bit, column address in 6-bit and page address in 1-bit. Further, the data D0WD3, D4WD6 input with the data selector 6 are selected to input them to RAM1W4 and the input data are latched at the data latch circuit 7.
COPYRIGHT: (C)1981,JPO&Japio
JP54091364A 1979-07-18 1979-07-18 Microcomputer data writing/reading method Expired JPS5939830B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54091364A JPS5939830B2 (en) 1979-07-18 1979-07-18 Microcomputer data writing/reading method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54091364A JPS5939830B2 (en) 1979-07-18 1979-07-18 Microcomputer data writing/reading method

Publications (2)

Publication Number Publication Date
JPS5616254A true JPS5616254A (en) 1981-02-17
JPS5939830B2 JPS5939830B2 (en) 1984-09-26

Family

ID=14024319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54091364A Expired JPS5939830B2 (en) 1979-07-18 1979-07-18 Microcomputer data writing/reading method

Country Status (1)

Country Link
JP (1) JPS5939830B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041156A (en) * 1983-02-25 1985-03-04 テキサス　インスツルメンツ　インコ−ポレイテツド Non-synchronous controller
JPS61190152U (en) * 1985-05-20 1986-11-27

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6041156A (en) * 1983-02-25 1985-03-04 テキサス　インスツルメンツ　インコ−ポレイテツド Non-synchronous controller
JPH0474745B2 (en) * 1983-02-25 1992-11-27
JPS61190152U (en) * 1985-05-20 1986-11-27
JPH0334921Y2 (en) * 1985-05-20 1991-07-24

Also Published As

Publication number Publication date
JPS5939830B2 (en) 1984-09-26

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