JPS6417509A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS6417509A
JPS6417509A JP62173072A JP17307287A JPS6417509A JP S6417509 A JPS6417509 A JP S6417509A JP 62173072 A JP62173072 A JP 62173072A JP 17307287 A JP17307287 A JP 17307287A JP S6417509 A JPS6417509 A JP S6417509A
Authority
JP
Japan
Prior art keywords
logical value
terminal
turned
changed
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62173072A
Other languages
Japanese (ja)
Inventor
Toshiyuki Kano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62173072A priority Critical patent/JPS6417509A/en
Publication of JPS6417509A publication Critical patent/JPS6417509A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE:To reduce the number of delay elements and to reduce also the area of a chip by connecting two MOS transistors(TRs) to the output of an inverter circuit to constitute a delay circuit. CONSTITUTION:When a signal impressed to an input terminal is changed from logical value '0' to '1', a P-MOS-TR 3 is turned off, an N-MOS-TR 5 is turned on and a logical value '0' is outputted from a terminal 4. When the signal impressed to the terminal 1 is changed from the logical value '1' to '0', the TR 3 is turned on and the TR 5 is turned off. At that time, the output of the inverter circuit 2 is changed from the logical value '0' to '1' and the output of the terminal 4 is also changed from the logical value '0' to '1', but the output change of the terminal 4 is delayed only by the sum of the delay time of the circuit 2 and the delay time of the TR 3. Namely, only the signal changing from the logical value '0' to '1' out of signals outputted from the terminal 4 is delayed.
JP62173072A 1987-07-13 1987-07-13 Delay circuit Pending JPS6417509A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62173072A JPS6417509A (en) 1987-07-13 1987-07-13 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62173072A JPS6417509A (en) 1987-07-13 1987-07-13 Delay circuit

Publications (1)

Publication Number Publication Date
JPS6417509A true JPS6417509A (en) 1989-01-20

Family

ID=15953685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62173072A Pending JPS6417509A (en) 1987-07-13 1987-07-13 Delay circuit

Country Status (1)

Country Link
JP (1) JPS6417509A (en)

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