JPS6417120A - Crt controller - Google Patents

Crt controller

Info

Publication number
JPS6417120A
JPS6417120A JP17438687A JP17438687A JPS6417120A JP S6417120 A JPS6417120 A JP S6417120A JP 17438687 A JP17438687 A JP 17438687A JP 17438687 A JP17438687 A JP 17438687A JP S6417120 A JPS6417120 A JP S6417120A
Authority
JP
Japan
Prior art keywords
memory
data
mpu
carried out
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17438687A
Other languages
Japanese (ja)
Inventor
Mitsuo Kurakake
Jiro Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP17438687A priority Critical patent/JPS6417120A/en
Publication of JPS6417120A publication Critical patent/JPS6417120A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE:To omit a pulse circuit for refresh by refreshing a memory with a access given from a processor in case a pseudo static RAM to a frame memory. CONSTITUTION:For a frame memory 1, the read signals for a CRT monitor are delivered periodically in each cycle T via a character generator 5. Meanwhile a writing action is carried out for replacement of the data given from a processor (MPU) and these replaced data are stored in the memory 1. In this case, the reading actions of a CRT are carried out each time against the cycle T and the read data are sent to the CRT monitor. While the writing actions are carried out via the MPU as necessary for replacement of data. Thus the memory 1 is refreshed by the signal received from a sequence circuit 2 and by means of the non-writing timing given from the MPU.
JP17438687A 1987-07-13 1987-07-13 Crt controller Pending JPS6417120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17438687A JPS6417120A (en) 1987-07-13 1987-07-13 Crt controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17438687A JPS6417120A (en) 1987-07-13 1987-07-13 Crt controller

Publications (1)

Publication Number Publication Date
JPS6417120A true JPS6417120A (en) 1989-01-20

Family

ID=15977703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17438687A Pending JPS6417120A (en) 1987-07-13 1987-07-13 Crt controller

Country Status (1)

Country Link
JP (1) JPS6417120A (en)

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