JPS641322A - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- JPS641322A JPS641322A JP62157209A JP15720987A JPS641322A JP S641322 A JPS641322 A JP S641322A JP 62157209 A JP62157209 A JP 62157209A JP 15720987 A JP15720987 A JP 15720987A JP S641322 A JPS641322 A JP S641322A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- gate
- control signal
- delaying
- output data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Pulse Circuits (AREA)
- Networks Using Active Elements (AREA)
Abstract
PURPOSE: To constitute a delay circuit inside an LSI, by using a gate, which is also used as a delay element, instead of a tap switching mechanism and supplying a gate control signal to the gate.
CONSTITUTION: In block 1, a control signal B is set to '0' with the shifting clock C of a shift register 9 and both output data QA and QB of the register 9 are '0' and, when the both output data are decoded by a decoding circuit 10, an output is made to the terminal 0 of the circuit 10. As a result, a gate control signal E becomes enable and a gate 5 is set to a signal passing state. Therefore, a signal D which is obtained by delaying a signal A by means of gates 1∼3 and 5 is outputted from the gate 5. In block 2, the control signal B is '1' and the shift register 9 is set to '1' by the shift clock C. Then the output data QA is '1' and QB is '0' and an output is made to the terminal 1 of the decoding circuit 10. As a result, a gate control signal G becomes enable and the signal D which is obtained by delaying the signal A at gates 1 and 7 is outputted. Therefore, the delaying time or phase of the signal can be controlled with a signal from the outside.
COPYRIGHT: (C)1989,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-157209A JPH011322A (en) | 1987-06-24 | delay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-157209A JPH011322A (en) | 1987-06-24 | delay circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS641322A true JPS641322A (en) | 1989-01-05 |
JPH011322A JPH011322A (en) | 1989-01-05 |
Family
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6275068B1 (en) * | 1999-12-22 | 2001-08-14 | Lucent Technologies Inc. | Programmable clock delay |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6275068B1 (en) * | 1999-12-22 | 2001-08-14 | Lucent Technologies Inc. | Programmable clock delay |
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