JPS641063A - Restoring method for logic circuit diagram - Google Patents

Restoring method for logic circuit diagram

Info

Publication number
JPS641063A
JPS641063A JP62066044A JP6604487A JPS641063A JP S641063 A JPS641063 A JP S641063A JP 62066044 A JP62066044 A JP 62066044A JP 6604487 A JP6604487 A JP 6604487A JP S641063 A JPS641063 A JP S641063A
Authority
JP
Japan
Prior art keywords
logic circuit
signal system
inverters
circuit diagram
recognized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62066044A
Other languages
Japanese (ja)
Other versions
JPH011063A (en
Inventor
Ryoichi Oe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62-66044A priority Critical patent/JPH011063A/en
Priority claimed from JP62-66044A external-priority patent/JPH011063A/en
Publication of JPS641063A publication Critical patent/JPS641063A/en
Publication of JPH011063A publication Critical patent/JPH011063A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To restore a logic circuit diagram easy to be recognized by a designer, by enabling a data signal system and a control signal system to be recognized, and performing separated wiring by distinguishing both systems so as to recognize their wiring separately.
CONSTITUTION: Inverters 9 and 10 are selected based on the connection information of the logic circuit diagram. Next, transmission gates (5W7) to which the output terminals of the inverters 9 and 10 are connected are selected. The inverters 9 and 10 are not wired directly with the data signal system consisting of transmission gates (5W8) other than the gates connected to the inverters 9 and 10, and another circuit device, and the wiring is shown by a coupler, and also, a logic circuit where they are arranged separately in separated positions can be obtained. Since the gates 5W8 are controlled so that they are energized when an input clock pulse CK is set at an L level, and are de- energized when the CK is set at an H level, the inverters 9 and 10 constitute the control signal system. Since the control signal system is arranged separately from the data signal system, the logic circuit diagram easy to be recognized can be obtained.
COPYRIGHT: (C)1989,JPO&Japio
JP62-66044A 1987-03-20 Logic circuit diagram restoration method Pending JPH011063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-66044A JPH011063A (en) 1987-03-20 Logic circuit diagram restoration method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-66044A JPH011063A (en) 1987-03-20 Logic circuit diagram restoration method

Publications (2)

Publication Number Publication Date
JPS641063A true JPS641063A (en) 1989-01-05
JPH011063A JPH011063A (en) 1989-01-05

Family

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