JPS5769306A - Programmable logic controller - Google Patents
Programmable logic controllerInfo
- Publication number
- JPS5769306A JPS5769306A JP55142611A JP14261180A JPS5769306A JP S5769306 A JPS5769306 A JP S5769306A JP 55142611 A JP55142611 A JP 55142611A JP 14261180 A JP14261180 A JP 14261180A JP S5769306 A JPS5769306 A JP S5769306A
- Authority
- JP
- Japan
- Prior art keywords
- data
- bus
- gate
- eor
- new
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Program-control systems
- G05B19/02—Program-control systems electric
- G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/052—Linking several PLC's
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/15—Plc structure of the system
- G05B2219/15018—Communication, serial data transmission, modem
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Multi Processors (AREA)
- Programmable Controllers (AREA)
Abstract
PURPOSE:To simplify the constitution of a data change exchanging part and at the same time to realize a high-speed exchanging action, by transmitting simultaneously the data change detection signals to a link but through each controller and exchanging the data to each other. CONSTITUTION:Both the new and old data NEW and OLD are read out of an input/output memory 4 and a reference memory 9 of a master device and a slave device respectively to be supplied to an exclusive OR circuit 11. Thus a data change signal (eor) is obtained from the circuit 11. The data (eor) is inverted by an inverter 12 and sent to a bus B1 in a link bus 10 at a time for both the master and slave devices. At the same time, the signal (eor) is applied to a gate 24 in the form of a control signal of the data NEW, and the change data new is sent to a bus B3 in the link 10 from the gate 24 simultaneously for both the master and slave devices. Furthermore the signal (eor) on the bus B1 is fetched into each device to be applied in the form of the control signals of both an inhibition gate 21 and a gate 22. At the same time, the data new on the bus B3 is also supplied to a gate 21 of each device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55142611A JPS5769306A (en) | 1980-10-13 | 1980-10-13 | Programmable logic controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55142611A JPS5769306A (en) | 1980-10-13 | 1980-10-13 | Programmable logic controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5769306A true JPS5769306A (en) | 1982-04-28 |
Family
ID=15319347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55142611A Pending JPS5769306A (en) | 1980-10-13 | 1980-10-13 | Programmable logic controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5769306A (en) |
-
1980
- 1980-10-13 JP JP55142611A patent/JPS5769306A/en active Pending
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