JPS6399612A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To obtain a variety of output frequencies with a simple constitution by inputting the set value of a frequency to one input terminal of an adder, further inputting its output to the other terminal through a latch, inputting a pulse becoming a reference frequency to the latch and obtaining the output frequencies from the output terminal of the adder. CONSTITUTION:The frequency set value N and the output from the latch R are inputted to the one input terminal A1 and the other terminal A2 of the adder FA, respectively. They are added and outputted to an addition output terminal B. If the added result carries over, a pulse is outputted to a carry over output terminal C. Everytime a clock pulse is inputted, the latch R fetches, holds and outputs the added result becoming the reference frequency. Its output is inputted to the input terminal A2 of the adder FA. By varying the frequency set value N, a host of output frequencies can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a frequency synthesizer that obtains an output frequency lower than the base TV frequency.

[Conventional technology]

Conventionally, when it was desired to obtain an output frequency lower than the reference frequency, a predetermined output frequency was obtained by connecting frequency dividers using flip-flops in multiple stages or by connecting shift registers in multiple stages.

[Problem that the invention seeks to solve]

The conventional frequency division method has a problem in that it requires a large number of flip-flops in order to obtain an output frequency sufficiently lower than the reference frequency. Also, with the shift register method, is it possible to select many different output frequencies? There was a problem with IH.

[Technical means to solve the problem]

The present invention has been made in view of the above problems, and consists of inputting a frequency setting value to one input terminal of an adder, and inputting the output of the adder to the other input terminal of the adder via a latch. However, a measure was taken in which a pulse serving as a reference frequency was input to the clock pulse input terminal of the latch, and the output frequency was obtained from the output terminal of the adder.

[Effect]

The adder FA has two input terminals Δ1 and A2, an output terminal B for the addition result, and a carryover output terminal C for the addition result, and the latch R has an input terminal Rin, an output terminal Rout, a clock pulse input terminal Rp, and an output terminal. Clear signal terminal Rc
Since there is
(7N is a power of 2), and when the clock pulse of nap is input to the clock pulse input terminal Rp of latch R, the addition result in adder F''A is expressed as S(n
＞, then the following formula holds true.

S (n)-8(n-1)→-N Here, if the output of latch R is cleared to 0 at the same time as the first clock pulse (n=1), S (1)
=N. Therefore, S (n) = n - N Here, when m clock pulses "I" are input to the latch R, the addition result at the adder F A becomes the maximum value 2M, and the carryover output terminal C Suppose that a pulse is output from S (m) = 2', so M-N-2' Therefore, M = 2'/N Therefore, let the frequency of the clock pulse be P (Hz), and the carryover output If the frequency of the pulse output from terminal C is F (Hz), then F=P/M(H2) Therefore, F=P-N/2' (Hz).

That is, by changing the value N input to the input terminal A1 of the adder FA, it is possible to obtain an output with a frequency of P - N/2' CH2] from the carryover output terminal C of the adder FA.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

In the drawing, F A is an 8-bit adder and R
is a 3-bit latch, and FF is a flip-flop.

F A is an adder having two input terminals AI and A2, an output terminal B, and a carryover output terminal C. R is a latch having an input terminal Rin, an output terminal Rout, a clock pulse input terminal Rp, and an output clear signal input terminal Rc.

Input the frequency setting value N to one input terminal A1 of the adder F A, input the output from the latch R to the other input terminal Δ2, and output the addition result of the above two input data to the addition output terminal B. However, when the addition result carries over, a pulse is output to the carryover output terminal C, and since the carryover output terminal C is connected to the output clear signal input terminal Rc of the latch R, the latch R outputs the output data. Let be O. Furthermore, the latch R takes in, holds and outputs the addition result every time a clock pulse serving as the reference frequency is input, and the output is input to the input terminal A2 of the adder FA. Then, the output signal from the carryover output terminal C is divided by a frequency of -7 by a flip-flop FF, shaped into a waveform with a duty ratio of 50%, and output.

For example, if the clock pulse frequency P is 128kHz,
If the frequency setting value N is 32 (=25), the adder FA
8 (=
A pulse is output from the carryover output terminal C every 21+/25)th clock pulse. That is, 16 (=
128/8) kHz is obtained. Next, the frequency division waveform is shaped by a flip-flop FF to 8 kHz.
The frequency of is obtained.

Similarly, if the frequency setting value N is 4, the adder F
A frequency of 1 kHz is obtained from the carryover output terminal C of A. Further, at this time, a frequency of 2 kHz is obtained from the seventh binote of the output terminal B of the adder FA, and a frequency of 4 k 11 z is obtained from the sixth binote.

In this way, various output frequencies can be obtained by variously changing the frequency setting value N.

Note that if it is desired to increase the frequency division ratio or to obtain many different frequencies, the number of bits M of the adder FA and latch R may be increased.

Further, by inputting the output of the adder FA to the flip-flop FF via a predetermined decoder, it becomes possible to obtain an even wider variety of output frequencies.

〔effect〕

The frequency synthesizer according to the present invention does not use a frequency divider but uses an adder and a latch, so it has the advantage of being able to obtain various output frequencies with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frequency synthesizer according to the present invention. FA, , Adder, R10, Latch, FF, . Flip-flop, PLL, reference frequency.

Claims (1)

[Claims] A frequency setting value is input to one input terminal of the adder, the output of the adder is input to the other input terminal of the adder via a latch, and a pulse serving as a reference frequency is input to the clock pulse input terminal of the latch. A frequency synthesizer that inputs , and obtains an output frequency from the output terminal of the adder.