JPH0653820A - Clock frequency dividing circuit - Google Patents

Abstract

PURPOSE:To make it possible to execute optional frequency division only by the use of one oscillation circuit by changing a frequency dividing ratio in each cycle. CONSTITUTION:This clock frequency dividing circuit is provided with a down counter C, a selection circuit S and a control circuit CRT. The down counter C counts up a set value and outputs two output signals when the counted value is the set value and a value next to the set value. Namely a clock inputted to an input terminal 1 is inputted to a down counter and counted. When the count value becomes '1' and an output (b) is turned to '0', an output (a) is turned to a high level. Two outputs of the down counter C are selected at a fixed rate by a selection circuit S and a control circuit CTR and the selected output is outputted from an output terminal O to obtain frequency division other than 1/n (n: natural number). In the case of attaining 2/9 frequency division e.g. 2 pulses are allowed to be outputted in each input of 9 clocks. Thereby frequency division can be attained by alternately executing 4 and 5 frequency division.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock frequency dividing circuit, and more particularly to a system using a digital circuit.

[0002]

2. Description of the Related Art A conventional clock divider circuit is shown in FIG. As shown in FIG. 6, a clock is input to the input terminal I. This signal is counted by the down counter C. In the down counter C, the written value is decremented by 1 each time the input signal rises, and when it becomes 0, the output terminal O becomes high level. By using this output as the write signal of the down counter C, the value of the frequency division ratio setting register R is written in the down counter C, and the counting is started again. By continuously performing this operation, 1 / the frequency of the clock input to the input terminal I
The frequency of R is output from the output terminal O.

[0003]

In this conventional clock frequency dividing circuit, the frequency dividing ratio cannot be any other than 1 / n (n: natural number).

Therefore, in a system such as a personal computer which requires a plurality of clocks, a plurality of clocks such as a system clock, a clock clock, a communication clock, and a display clock are used, so that separate oscillator circuits are required. .

An object of the present invention is to provide a clock frequency dividing circuit having a circuit composed of one oscillator circuit.

[0006]

In order to achieve the above object, a clock frequency dividing circuit according to the present invention is a clock frequency dividing circuit having a counter, a selection circuit and a control means, and the counter is a setting circuit. The counter that outputs two output signals that become active when the count value is the set value and when the count value is the next value, and the selection circuit determines which of the two output signals of the counter is output. One of them is selected, and the control means counts one selected output signal and controls the selection circuit according to the count number.

Further, the frequency division ratio is determined according to the ratio at which the selection circuit and the control means select the output of the counter.

[0008]

[Operation] By changing the division ratio for each cycle,
Frequency division is performed at an arbitrary frequency division ratio.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, the clock input to the input terminal I is input to the down counter C and counted.
As a result of this counting, the output b becomes high when it becomes 1, and the output a becomes high when it becomes 0. By selecting the two outputs of the down counter C by the selection circuit S and the control circuit CTR at a fixed ratio and outputting them from the output terminal O, frequency division other than 1 / n (n: natural number) is possible. Become.

As an example, FIG. 2 shows an example of a circuit for realizing the 2/9 frequency division. In order to realize the 2/9 frequency division, it is sufficient to output 2 pulses for every 9 clocks input. Therefore,
This can be achieved by alternately performing division by 4 and division by 5. Figure 2
In the circuit shown in, the frequency division ratio R is set to 4 (100 in binary). In the down counter C, the written value is 1 each time the clock is input from the input terminal I.
Are subtracted one by one. Therefore, after the frequency division ratio R is written in the down counter C, the “= 1” signal becomes high level at the 4th clock and the “= 0” signal becomes high level at the 5th clock.

The output level of the control circuit CTR is inverted every time the output terminal O goes high. In the selection circuit S, when the output of the control circuit CTR is low level, "=
When the "0" signal is high level, the "= 1" signal is selected and output.

As a result, the "= 0" signal and the "= 1" signal are alternately output to the output terminal O, and 2/9 frequency division can be realized. The down counter C is written with a value in which the frequency division ratio R is set every time the output terminal O goes high. The operation of this circuit is shown in FIG.

Next, FIG. 4 shows an example of a circuit in which an arbitrary frequency division ratio can be set. In this example, the x / y frequency division ratio can be set without being restricted by the bit lengths of the frequency division ratio setting registers (R1, R2, R3). However, x,
y is a natural number and has a relationship of y / x.

Frequency division ratio setting registers (R1, R2, R
The value set in 3) is calculated by the following procedure.

[0016]

[Equation 1] Set the value in each register. R1: a, R2: y-ax, R3: x

The operation of each block of the circuit shown in FIG. 4 will be described below. The clock input from the input terminal I is input to the down counter C. This down counter C
Latches the contents of the frequency division ratio setting register R1 in synchronization with the input of the next count when the output of the selection circuit S1 is active (high level in this embodiment).

When the output of the selection circuit S1 is active (low level in this embodiment), the latched content is decremented by 1 for each count input, and when the result is 1, "= 1". When the "signal is 0, the" = 0 "signal is active.

In the selection circuit S1, the "= 0" signal is selected when the output of the control circuit CTR is inactive, and the "= 1" signal is selected and output from the output terminal O.

The control circuit CTR operates every time the output of the selection circuit S1 changes from active to inactive. First, the content selected by the selection circuit S2 is written in the temporary storage register TMP. Next, the contents written in the temporary storage register TMP and the contents of the frequency division ratio setting register R2 are added by the adder circuit ADD. This result (TMP +
The content of the division ratio setting register R3 is subtracted from the subtraction circuit S
Subtract by UB.

As a result, when (TMP + R2-R3) is negative, the "BORROW" signal is active (high level in this embodiment), and inactive (low level in this embodiment) when positive. ). This "BORRO
The W "signal is directly output from the control circuit CTR. At the same time, it is input to the selection circuit S2 in the control circuit CTR.

The selection circuit S2 outputs the result (TMP + R) of the subtraction circuit SUB when the "BORROW" signal is active.
2-R3), adder circuit ADD when inactive
The result (TMP + R2) is selected and output. This output is written to the temporary storage register TMP at the next operation timing of the control circuit CTR.

The operation of this circuit is as follows: input frequency: 10 MH
z (CPU clock frequency), output frequency: 3276
A case of 8 Hz (clock frequency of the built-in clock) will be described as an example.

First, the value set in each division ratio setting register is

[Equation 2]

Assume that the value of the temporary storage register TMP is 0 and the value of the down counter C is 305 in the initial state (point in FIG. 5). At this time, (TMP + R2-R3)
Becomes negative and the "BORROW" signal becomes active. Therefore, the selection circuit S1 selects the "= 1" signal. This signal becomes active for one clock at the 305th count of the input clock. Therefore, at the 306th clock, 305 is written in the down counter C and 45 (TMP + R2) is written in the temporary storage register. This completes the first frequency division with a division ratio of 1/305.

Even in the second division, (TMP + R2-R
Since 3) is negative, the input clock is divided by the value of R1 (division ratio 1/305).

In this way, the frequency division progresses, the TMP becomes 225 at the sixth time, and (TMP + R2-R3) becomes positive. Therefore, the "= 0" signal is selected by the selection circuit S2, and the frequency division ratio is

[Equation 3] Becomes Further, when this frequency division is completed, the value written in TMP becomes 14 (TMP + R2-R3).

By continuously performing the above operation,
Frequency division ratio of clock (10MHz) from input terminal I 25
The frequency of 6/78125 (32768 Hz) can be output from the output terminal O.

[0029]

As described above, according to the present invention, it is possible to arbitrarily divide the frequency by changing the frequency division ratio for each cycle, and in the system which currently uses a plurality of oscillation circuits, The effect is that only one circuit is required.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram when the frequency dividing ratio of the frequency dividing circuit shown in FIG. 1 is 2/9.

3 is a signal waveform diagram of each part when the frequency divider circuit of FIG. 2 is operated.

FIG. 4 is a block diagram showing another embodiment of the present invention.

5 is a diagram showing a value of each register when the frequency dividing circuit in FIG. 4 is operated.

FIG. 6 is a block diagram showing a conventional frequency divider.

[Description of Codes] a counter = 0 output b counter = 1 output C down counter CTR control circuit I input terminal O output terminal R division ratio setting register S selection circuit

Claims (2)

[Claims] 1. A clock frequency dividing circuit having a counter, a selection circuit, and a control means, wherein the counter counts a set value, and when the count number is the set value and the next value. The counter that outputs two output signals that become active at the time of, and the selection circuit select either one of the two output signals of the counter, and the control means selects the selected one output signal. Count
A clock frequency divider circuit for controlling the selection circuit according to the count number. 2. The clock frequency dividing circuit according to claim 1, wherein the frequency dividing ratio is determined according to a rate at which the selection circuit and the control means select the output of the counter.