JPS63231390A - Video synchronous signal generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] A selection circuit that selects one of preset initial setting values and supplies it to a comparison circuit, and a counter that integrates clocks, and the integrated clock value is supplied from the selection circuit. Each initial setting value is reset by resetting the counter each time it matches the set value, switching the selection circuit using the pointer, and comparing the new initial setting value and the new lock cumulative value in the comparator circuit. This is a synchronization signal generation circuit with a simplified circuit configuration, which allows one comparison circuit to be shared for comparing the clock integrated value and the clock integrated value.

[Industrial application field]

The present invention relates to improvements in video synchronization signal generation circuits.

For example, in order to display characters, graphics, etc. on a display device, a display control device generates various driving signals necessary for displaying characters, graphics, etc. on an actual display device from character information and graphic information stored in a storage device. Output.

These signals include video synchronization signals, address signals for video RAM, and the like.

Video RAM'M is a device that stores video information, and has a storage device corresponding to each point on the display screen. Enables display of figures.

The address signal for the video RAM is generally a -address signal that corresponds to one address on the display surface.

The mask clock used for the display control device is supplied in synchronization with the output address signal, so in order to display arbitrary characters on one line on the display surface and with an arbitrary number of lines, a video synchronization signal is required. It is desirable that it can be set arbitrarily depending on the number of clocks.

In order to set the display range of the screen, it is also necessary to generate a blank signal, and it is desirable that the front porch and back porch extending before and after the synchronization signal, the effective width provided between the blank signals, etc. can be arbitrarily set.

[Conventional technology]

FIG. 5 is a circuit diagram of a conventional synchronization signal generator. In the illustrated case, a synchronization signal and a blank signal are generated. In contrast to the synchronization signal, the blank signal has a front porch and a bank porch, and an effective width is provided between adjacent blank signals. Signal widths are stored in registers 1 to 4 in order to determine the on/off points of the sync signal and the blank signal.

Next, adders 6 to 8 add the values stored in the registers in order, and provide the added values to comparison circuits 11 to 14 in order.

9 is a counter, and the clock integrated value is sent to each comparison circuit (11 to
14).

Comparison circuit 11 compares the number of ■ given from register 1 and the clock integrated value, and generates output C when a match is found. Also, the comparator circuit 12 is connected to the register 1 in the adder 6.
The value obtained by adding the value of ■ and the value of ■ from the register 2 is compared with the integrated value of the counter 9, and when they match, an output of D is generated.

Similarly, in the last comparison circuit 14, each register 1
When the total value of .about.4 (■+■+■+■) and the clock integrated value match, a signal is generated.

Here, the output of the comparison circuit 14 resets the counter 9 and restarts the next clock calculation.

In this way, the blank signal and the synchronization signal are repeatedly turned on and off by the output signals of C, D, E, and F, and the synchronization signal is generated.

FIG. 6 shows the waveforms of the synchronization signal (i) and blank signal (if) generated in the circuit of FIG.

In the figure, 1 is a blank signal portion that is a front porch before the synchronization signal, and this value is stored in register 1 in advance as ■. Similarly, 2 is the synchronization signal width ■, 3 is the back porch width ■, and 4 is the valid period width ■.
4 is stored.

The rise of the synchronizing signal (i) is caused by the fall of the cent signal C1, the fall of the blank signal by the cent signal D1 is caused by the reset signal E, and the rise of the blank signal is caused by the cent signal F.

[Problem that the invention seeks to solve]

In the conventional synchronous signal generator described above, the number of comparison circuits and adders must be increased in proportion to the number of sets of signals to be generated and the number of reset points, which has the disadvantage of increasing the circuit size and complexity. .

[Means for solving problems]

The above problem is solved by the selector 2 which selects one of the preset initial values, as shown in the principle diagram of the present invention in FIG.
5. Counter 27 for accumulating the number of clocks, selector 25
a comparison circuit 31 that compares the value supplied from the clock integrated value with the clock integrated value, generates a match signal, and resets the counter 27;
The selector 25 selects the next value based on the match signal from the comparison circuit 31.
This problem is solved by the video synchronization signal generation circuit of the present invention, which includes a pointer circuit 28 that selects a pointer circuit.

[Effect]

According to the present invention, a signal is supplied from the pointer circuit 2B to the selector 25, and the selector 25 selects one value from among the initial setting values 1 to n of the register 20 and supplies it to the comparison circuit 31. Starts new clock integration from the reset state. The comparison circuit 31 compares the integrated value B of the clock 5 by the counter 27 with the initial setting value given from the selector 25, and if A=B matches, sends a match signal to the counter 27, pointer 28, and selector 26. The counter 27 is reset, the pointer 28 is counted by the clock 5, and the new select value of the selector 25, 26 is output.

Initially, the selectors 25 and 26 were connected to contact position O, and the initial set value at the 0 position was connected from the register 20 to the comparator circuit 31, but now it was switched to contact position 1, and the next set value was transmitted from the register 20. Connect to comparison circuit 31.

Thereafter, switching is performed in the same manner until the contact position n reaches the initial setting value.

In addition, the counting output of the pointer 28 is also supplied to the selector 26, which switches the contact to the On position, and depending on the contact position, sends a synchronization signal, blank signal, etc. from the Korg 32 to the center,
Generates a signal to reset.

In this case, the comparison circuit (31) is used to compare each initial setting value set in advance with the clock, and is also used for determining each signal width, so only one comparison circuit is required, and the configuration is simple. Become. Further, the width can be arbitrarily changed by the initial setting of the serge resistor, making it easy to generate a synchronization signal wave with a variable width.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 to 4.

FIG. 2 is a circuit diagram of a video signal generator according to an embodiment of the present invention for generating a synchronization signal and a blank signal similar to the conventional example.

In the figure, 21 to 24 are D-shaped registers in which initial setting values are stored.

The initial setting values are front porch width, sync signal width, bank porch width, effective width, etc. 21 is front porch width ■,
22 is a synchronization pulse width (synchronization signal width) (2), 23 is a pack pouch width (2), and 24 is an effective width (2).

25 and 26 are selectors, 26 selects and outputs one of the four outputs, and 27 sends one output to one of the four outputs.

The counter 27 is a counter that can count up to the maximum value of the values set in the registers 21-24.

The pointer 28 consists of a gate 30 and a counter 29. In this embodiment, the counter 29 consists of a counter that counts 0 to 3. The output is used for switching control of selectors 25 and 26.

Comparison circuit 31 generates a high level signal at its output when the values of inputs A and B match.

The operation of the circuit is as follows.

When the outputs ■ and ■ of the counters 27.29 are both 0, the selector 25 selects the register 21 and the value of ■ is set to the selector 25.
The output is That is, ■−■.

Next, clock 5 is counted by counter 27, and counter 2
7 is equal to the output ■ of the selector 25, so that ■=■, and when ■=■−■, the output ■ of the comparator circuit 31 becomes high level. At this time, the value of the output ■ of the counter 29 is 0.
Therefore, the selector 26 applies the high level signal (■) to the top gate of the gate 33, and the high level signal (■) to the cent reset type register 34.
As a result, the register 34 outputs a synchronization signal set signal.

At the same time, the clock 5 is input to the counter 29 via the gate 30, so the output 2 of the counter 29 becomes 1. This signal is supplied to the selector 25, and the selector 25
selects the output ■ of the register 22.

The output ■ of the selector 25 becomes equal to the value of ■. -Also,
Since the counter 27 is reset by the match signal from the comparison circuit 31, the value of ■ becomes O.

Therefore, the counter 27 performs the calculation again by inputting the clock 5, and compares it with the value of (2) given from the selector 25 in the comparison circuit 31.

Repeating this process, the pointer 28 becomes the counter 29.
By the counting operation of O to 3 at , a synchronization signal, a blank signal cent, and a reset signal are output.

The generation positions of the cent and reset signals in the above embodiment can be easily changed by the initial setting values of the registers.

Furthermore, the present invention is not limited to the generation of synchronization signals and blank signals, but can be extended to other similar waveform generation circuits.

〔Effect of the invention〕

According to the present invention, a simple circuit configuration including a selector for selecting an initial setting value, a counter for accumulating clocks, a pointer circuit for instructing switching of the selector, and a comparison circuit is used to select the initial setting value. Provides a video synchronization signal generator that can easily generate signal waveforms,
Its effects are extremely large.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a circuit diagram of a video synchronization signal generator according to an embodiment of the present invention, Fig. 3 is an operation waveform diagram of the circuit shown in Fig. 2, and Fig. 4 is the circuit shown in Fig. 2. FIG. 5 is a circuit diagram of a conventional synchronizing signal generator, and FIG. 6 is a waveform diagram of an example of a generated synchronizing signal. In the figure, 1-4.20.21-24 are registers, 5 is a clock, 6-8 are adders, 9.27.29 are counters, 11-14.31 are comparison circuits, 25.26 are selectors, 28 pointers , 30 is a gate, 32 is a Korg, 33 is a gate, and 34.35 is a register. Figure 1 Figure 6 Figure ■-0-■, @, 0.0-〇 Figure 2 Flowchart of circuit operation Figure 4 Figure 5

Claims (1)

[Claims] Selector (2) for selecting one of the preset initial setting values
5), a counter (27) that integrates the number of clocks, a comparison circuit (31) that compares the value supplied from the selector (25) and the clock integration value, generates a match signal, and resets the counter (27); A video synchronization signal generation circuit comprising: a pointer circuit (28) that causes a selector (25) to select the next value in response to a match signal from the circuit (31).