JP3382020B2 - Timing control circuit for signal generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator timing control circuit used for a baseband signal generator of a microwave digital modulator such as a multi-phase PSK modulator or an FSK modulator.

[0002]

2. Description of the Related Art A baseband signal generator used in a conventional microwave digital modulator is as shown in FIG.
ROM (read only memory) 11 for storing waveform data,
An address counter 12 for controlling the read address of the ROM 11 is provided. Waveform data such as a sine wave is stored in the ROM 11 in advance. The address counter 12 has an initial value set by the preset data Pin, counts the clock pulse CK from the initial value while the input data Din is at the high level, and sends the count value to the ROM 11 as a read address.

By the way, the baseband signal generator having the above structure is designed to reset the address counter 12 by the rising edge of the input data Din, and the rising edge timing of the input data Din before the rising edge of the clock pulse CK. Must be set to.
However, when the set frequency of the baseband signal becomes high and the waveform data reading speed becomes high, the frequency of the clock pulse CK also becomes high, so that its timing control becomes extremely difficult.

[0004]

As described above, in the signal generator used in the baseband signal generator of the conventional digital modulator, it is particularly difficult to control the reset timing as the set frequency becomes higher. Is becoming.

The present invention has been made to solve the above problems, and provides a timing control circuit for a signal generator capable of resetting at an accurate timing even if the waveform data reading speed becomes high. With the goal.

[0006]

In order to achieve the above object, the present invention provides a memory for storing waveform data and an address counter for generating a read address of the memory by counting clock pulses only during a data input period. In a signal generator timing control circuit for controlling a clock pulse supply timing and a reset timing, the input data is shifted by one symbol and two symbols, and first and second
Shift register for outputting the data of the above, and the first and second
A first arithmetic circuit for calculating the exclusive OR of the data of
A second arithmetic circuit that calculates the logical product of the output of this circuit and the clock pulse to derive it to the clock terminal of the address counter, an inverter circuit that inverts and outputs the input data, the input data and the inverter circuit. A third arithmetic circuit for calculating a logical product with the output of the second arithmetic circuit; The delay circuit of No. 1 is provided.

[0007]

In the timing control circuit for the signal generator having the above structure, the shift register shifts by 1 or 2 symbols to generate the first and second data, and the first arithmetic circuit calculates the exclusive OR of the two. Then, the input data is delayed by one symbol to obtain data. Then, the logical product of the output data and the clock pulse is calculated by the second arithmetic circuit, and the clock pulse is derived to the address counter only during the data input period so that the clock pulse is not derived before the rising edge of the data. On the other hand, the inverter circuit inverts the input data, and the third arithmetic circuit calculates a logical product with the input data to generate a pulse by utilizing the inversion processing time of the inverter circuit.
In the delay circuit of, the address counter is delayed from the end of counting the last clock pulse until just before the new clock pulse is derived, and this is supplied to the address counter as a reset signal.
The address counter is reset before the clock pulse is input.

[0008]

Embodiments of the present invention will be described in detail below with reference to the drawings. However, in FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted. FIG. 1 shows a configuration in which the present invention is applied to the baseband signal generator shown in FIG. 4, and input data Din is input to the shift register 21. The shift register 21 has a synchronization clock S synchronized with one symbol of the input data Din.
CK is input, and according to the synchronous clock SCK, input data is shifted by one symbol time and output from the QA terminal, and further shifted by one symbol time and output from the QB terminal.

The QA terminal and Q of the shift register 21
The data D1 and D2 output from the B terminal are both EX-O
It is input to the R (exclusive OR) circuit 22, and its operation output D3 is supplied to one input end of the first AND (logical product) circuit 24 via the first delay circuit 23. This AND
The clock pulse CK is supplied to the other input terminal of the circuit 24, and its operation output is supplied to the clock terminal of the address counter 12 as the count pulse CK '.

On the other hand, the input data Din is the second AND
It is directly supplied to one input terminal of the circuit 25, inverted by the inverter circuit 26 (Din-), and supplied to the other input terminal of the second AND circuit 25. This second AND
The operation output P of the circuit 25 is supplied as a reset signal SR to the reset terminal of the address counter 12 via the second delay circuit 27.

The operation of the above configuration will be described below with reference to FIG. Note that the delay time of the first delay circuit 23 is neglected here for simplification of description.
Now, assume that the synchronous clock SCK and the data Din shown in FIGS. 2A and 2B are input. Shift register 21
Is the synchronization clock S as shown in FIGS. 2 (c) and 2 (d).
Data Din is shifted one symbol at a time according to CK, and QA
, QB terminals output data D1 and D2.

EX in which these data D1 and D2 are input
-OR circuit 22 calculates the exclusive OR of both,
As shown in (e), the input data Din is delayed by one symbol to obtain the data D3.

Here, the clock pulse CK is as shown in FIG.
2G, the output data D3 of the EX-OR circuit 22 and the output of the first AND circuit 24 to which the clock pulse CK is input are as shown in FIG. The clock pulse CK is delivered to the address counter 12 only during the high level period. That is, the clock pulse CK is not derived before the rising edge of the data D3.

On the other hand, the data Din input to the inverter circuit 26 is inverted and output, but the output inversion timing is slightly delayed from the input inversion timing as shown in FIG. 2 (h). Therefore, when the second AND circuit 25 takes the logical product of the input data Din and the inverted output Din- of the inverter circuit 26, the pulse P shown in FIG. 2 (i) is obtained.

Then, the pulse P thus obtained is obtained.
Is delayed by the second delay circuit 27 so that the clock pulse CK 'immediately before the clock pulse CK' shown in FIG. 2 (g) appears in the period from when the address counter 11 finishes counting to immediately before the output. This is supplied to the address counter 12 as a reset signal SR. As a result, the address counter 12 is reset before the clock pulse CK 'is input.

Here, the delay time of the second delay circuit 27 may be adjusted within the range of one cycle of the clock pulse CK shown in FIG. 2 (f), and further, the first delay circuit 23.
By delaying the EX-OR output as appropriate, the adjustment range can be expanded. Of course, the first delay circuit 2
It does not matter if 3 is omitted.

Therefore, the timing control circuit having the above configuration can reset the waveform data at a precise timing even if the waveform data reading speed becomes high. By the way, in the above embodiment, the reset pulse is generated depending on the inversion processing time of the inverter circuit 26.
If the pulse width is too short, as shown in FIG.
If the output of the inverter circuit 26 is supplied to the AND circuit 25 via the buffer gate 28, the pulse width can be widened.

In the case where several kinds of waveform data read speeds can be selected, a plurality of delay circuits 27 (three in FIG. 3) are used as the second delay circuits 27 as shown in FIG.
1 to 273 are provided in parallel, the delay time of each delay circuit 271 to 273 is made to correspond to each waveform data reading speed, and at the same time as the frequency selection of the clock pulse CK, the output pulse of the corresponding delay circuit is selected by the selector 29 according to the selection control signal. May be selectively derived to the address counter 12. The present invention is not limited to the above embodiment,
Needless to say, the present invention can be implemented in the same manner even if various modifications are made without departing from the scope of the present invention.

[0019]

As described above, according to the present invention, it is possible to provide a timing control circuit for a signal generator capable of resetting at accurate timing even if the waveform data reading speed becomes high.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a signal generator timing control circuit according to the present invention.

FIG. 2 is a timing waveform chart for explaining the operation of the above embodiment.

FIG. 3 is a block circuit diagram showing the configuration of another embodiment according to the present invention.

FIG. 4 is a block circuit diagram showing a configuration of a baseband signal generator used in a conventional digital modulator.

[Explanation of symbols]

11 ... ROM for waveform data storage, 12 ... Address counter, 21 ... Shift register, 22 ... EX-OR circuit, 2
3 ... 1st delay circuit, 24 ... 1st AND circuit, 25 ...
Second AND circuit, 26 ... Inverter circuit, 27, 27
1-273 ... Second delay circuit, 28 ... Buffer gate,
29 ... Selector.

Claims (4)

(57) [Claims] 1. A clock pulse supply timing for a signal generator comprising a memory for storing waveform data and an address counter for generating a read address of the memory by counting clock pulses during a data input period. In a timing control circuit for a signal generator for controlling reset timing, a shift register for shifting the input data by 1 symbol and 2 symbols to output first and second data, and a shift register for the first and second data. First to calculate exclusive OR
A second arithmetic circuit for calculating a logical product of the output of the circuit and the clock pulse to derive the logical product to the clock terminal of the address counter; an inverter circuit for inverting and outputting the input data; A third arithmetic circuit for calculating a logical product of the data and the output of the inverter circuit, and delaying the output of this circuit at least before deriving a clock pulse of the second arithmetic circuit to reset the address counter as a reset signal. A timing control circuit for a signal generator, comprising: a first delay circuit leading to a terminal. 2. The timing control for a signal generator according to claim 1, further comprising a second delay circuit for delaying an output of the first arithmetic circuit and deriving it to the second arithmetic circuit. circuit. 3. The timing control circuit for a signal generator according to claim 1, further comprising delay means for delaying the output of the inverter circuit and deriving it to the third arithmetic circuit. 4. A plurality of delay devices are arranged in parallel as the first delay circuit, and the delay time of each delay device is set in accordance with the selected frequency of the clock pulse.
2. The timing control circuit for a signal generator according to claim 1, wherein the output of the corresponding delay device is derived as a reset signal at the same time when the frequency of the clock pulse is selected.