JPS6214193A - Display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a display control device that displays a dot pattern, and more particularly to a display control device that enlarges and displays original pixels.

(Prior Art) Conventionally, when enlarging a display screen, video data stored in a video data storage unit is first read out to a processing device, and then
Processing the video data for enlarged display 1. Then again,
A method has been adopted in which enlarged display is performed by writing manipulated video data to a video data storage section.

(Problems to be Solved by the Invention) The above-mentioned conventional display control bag (l) performs enlarged display by writing the manipulated video data into the video data storage unit again, so when performing enlarged display, This method requires the intervention of software as described above, and has the drawback of lowering processing efficiency.

An object of the present invention is to provide a display control bag which eliminates the above-mentioned drawbacks by using an enlargement mode flip-flop and compensation/vertical enlargement register to realize enlarged display, and which eliminates the need for software intervention. The aim is to provide fl.

(Means for Solving the Problems) A display control device according to the present invention includes a video data storage section, an address generation section, an address register means, a counter means, an adder, an enlargement mode clip-flop, and a pair of It is configured to include a vertical/horizontal expansion register, a pair of frequency dividing circuits, a parallel/serial conversion register, and a pair of switching circuits.

The video data storage unit is for storing data to be displayed on the display device.

The address generation section is for generating an address for the video data storage section.

The address register means is for holding the address sent out from the address generator.

The counter means is operated to count each time data is read out from the video data storage section and to be reset when the display device returns horizontally.

The adder is for adding the contents of the address register means and the contents of the counter means.

The enlargement mode clip flop is for instructing enlarged display.

A pair of vertical/horizontal expansion registers are for indicating the vertical/horizontal expansion ratio, respectively.

The pair of frequency divider circuits are for frequency dividing the clock in accordance with the expansion ratio of the pair of vertical/horizontal expansion registers.

The parallel/serial conversion register is for converting the parallel data that can be sent out from the video data storage unit into serial data and sending it to the display device.

The pair of switching circuits is for switching between the clock and the output of the pair of frequency dividing circuits according to the instruction of the enlargement mode 7s7j7, and supplying the clock to the address generator and the parallel/serial conversion register.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an explanatory diagram showing an example of enlarged display according to the present invention, in which the original pattern on the left is enlarged twice in the horizontal direction and 3 times in the vertical direction.
If you enlarge it twice, it will look like the display on the right. In this way, the present invention allows for vertical and horizontal expansion independently by an integer multiple.

Next, a specific circuit will be explained with reference to FIGS. 2 to 4.

FIG. 2 is a block diagram showing an embodiment of the display control device according to the present invention, FIG. 8 is a time chart showing horizontal expansion in the device shown in FIG. 2, and FIG. 3 is a time chart showing vertical enlargement in FIG.

In Figure 12, 1 is an address generation section, 2 is an upper address register, 5 is a lower address register, 4 is a counter, 5 is an adder, 6 is a video data storage section, and 1 is a parallel/
Serial conversion register, 8 is an oscillator, 9 is a horizontal blanking pulse generator, 10 is a vertical expansion register, 11Vi horizontal expansion register, 12.13 is a frequency dividing circuit, 14 is an expansion mode flip-flop, 15.16 is a switching circuit It is.

In the description of this embodiment, two times in the horizontal direction and three times in the vertical direction will be considered as specific enlargement ratios.

First, horizontal expansion will be explained.

When instructing horizontal expansion, the expansion mode flip-flop 14 is set, and the horizontal expansion register 11 is set to an integral multiple (n=2).

Correspondingly, an oscillator output is provided from the clock oscillator 8 to the frequency dividing circuit 13 via the output signal line 11. As a result, a clock whose frequency is doubled by the frequency dividing circuit 13 is generated on the signal line 19, and passes through the switching circuit 16 to parallel/
Data sent to the serial conversion register 7 to be sent to the display device is controlled. At this time, if the enlargement mode flip 7Rozzo 14 is not set, the switching circuit 16 enters the normal clock mode (see il+ in FIG. 3), and the original pattern is displayed without being enlarged. but,
When the expansion mode flip 20 knob 14 is set, the switching circuit 16 outputs the output signal 111 of the frequency dividing circuit 13.
9 (see FIG. 8(2)), the output signal line 21 of the parallel/serial conversion register 1 becomes as shown in FIG. 3 (31) and is displayed with twice the length of the original pattern.

Next, a case where the vertical direction is enlarged will be explained. Similar to the horizontal enlargement, first the enlargement mode flip 70 7 14 is set, and the enlargement rate (m=
3) shall be set. Normally, when no vertical expansion is instructed, a normal clock is sent to the address generator IK via the signal line 18. At this time,
The values of address registers 2, 5 and counter 4 are as shown in FIG. 4, 121 and +31, respectively, and the address set signal on signal line 23 is sent out as shown in FIG. 4(1). Therefore, the output sent from the adder 5 to the signal line 25 by the output of the lower address register S and the counter 4 becomes the address of the video data storage section 6 (
Figure 4 (see 41).

Next, when expanding vertically, use the vertical expansion register 10.
A clock frequency-divided by the frequency dividing circuit 12 is sent to the address generating section 1 through the signal line 20 and the switching circuit 16. Address generator 1 sends out the clock shown in FIG. 4(5) and the address shown in FIG. 4(6), which are set in upper address register 2 and lower address register 3, respectively. The counter 4 is counted up every clock as shown in FIG. 4 (7), and is reset by a reset signal sent from the horizontal blanking pulse generator 9.

Therefore, the address of the Eirin data storage unit 6 that has passed through the adder 5 is as shown in FIG.
The same address as in the second and third video is generated again, and the same video data is displayed and enlarged in the vertical direction.

(Effects of the Invention) As explained above, the present invention uses an enlargement mode flip-flop and horizontal/vertical enlargement registers to realize enlarged display, thereby eliminating the need for software intervention. It has the effect of improving overall processing efficiency and making it easier to get pregnant.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram showing an example of enlarged display according to the present invention. FIG. 2 is a block diagram showing an embodiment of a display control device according to the present invention. Figure @3 is a time chart showing horizontal expansion. FIG. 4 is a time chart showing expansion in the vertical direction. 1. Address generator 2.3 Address register 4 Fist counter 5 - Adder 6 Video data storage section 1 Parallel/serial conversion register 8 Oscillator 9・・Horizontal retrace pulse generation unit 10 ・・Vertical expansion register 11-φ・Horizontal expansion register 12.15φe・Frequency divider circuit 14-・・Expansion mode flip 20 15.16・・
・Switching circuit

Claims (1)

[Claims] a video data storage section for storing data to be displayed on a display device; an address generation section for generating an address for the video data storage section; and an address for holding the address sent from the address generation section. a register means, a counter means for counting each time data is read from the video data storage section and operating to be reset at the time of horizontal retrace of the display device, contents of the address register means and the counter; an adder for adding the contents of the means, an enlargement mode flip-flop for instructing enlarged display, a pair of vertical/horizontal enlargement registers for indicating the vertical/horizontal enlargement ratio, respectively; a pair of frequency divider circuits for frequency dividing a clock in accordance with the enlargement ratio of the vertical/horizontal enlargement register; and a pair of frequency dividing circuits for converting parallel data sent from the video data storage section into serial data and sending the serial data to the display device. and a parallel/serial conversion register for switching between the clock and the output of the pair of frequency dividing circuits according to instructions from the expansion mode flip-flop and supplying the same to the address generation section and the parallel/serial conversion register. A display control device comprising a pair of switching circuits.