JPS6012581A - Display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a display device for displaying characters and the like.

Conventional configurations and their problems In recent years, display devices have tended to become larger and have larger capacities.
Accordingly, display devices are required to have many display functions. For example, in a word processor, the display may be
The ability to enlarge from Figure (a) as shown in Figure (b) has become indispensable.

FIG. 2 shows a block diagram of a conventional liquid crystal display device. In FIG. 2, 1 is a timing generation circuit, 2 is a parallel-to-serial conversion circuit, 3 and 4 are shift registers, and 5 is a timing generation circuit.
is a latch Φ driver circuit, 6 is a counter circuit, 7 is a dot matrix liquid crystal panel with m dots horizontally and n dots vertically, 8 is an external bag [, and N is display data from the host computer.

The operation of the liquid crystal display device configured as described above will be described below.

Parallel display data 8 is transferred from an external device, such as a host computer, to the parallel-to-serial conversion circuit 2. The clock signal from the timing generation circuit 1 is input to the clock input terminal 2a of the parallel/serial conversion circuit 2 and the clock input terminal 3a of the shift register 3. Based on this clock signal, the clock signal is input to the parallel/serial conversion circuit 2.
Data output from the serial input terminal 3C is transferred to the shift register 3. Data transfer between parallel/serial conversion circuit 2 and shift register 3 is performed in synchronization with a clock signal. Number of pixels on the horizontal axis of the liquid crystal panel 7 m
That is, the number of bits in the shift register 3 is counted by the counter 6, and the signal generated when the count is finished (for example, the signal at the carry-1 terminal) is input to the latch input terminal 5a of the latch/driver circuit 5, thereby being transferred to the shift register 3. (5) Data 10 on the horizontal axis is taken into the latch driver circuit 5, converted to a display signal voltage, and sent to the signal line of the liquid crystal channel 7. At the same time, by inputting the signal from the counter 6 to the clock terminal 4a of the shift register 4, the scanning line selection signal 9 is transferred to the liquid crystal panel 7 in synchronization with the data transfer on the horizontal axis, and n scanning lines are 1 selected from
A dot on the scan line of the book is displayed.

However, with the above configuration, when enlarging the display, the only way to enlarge the display is to control the input data 8 shown in FIG. 2 with an external device, which has the drawback of placing a heavy burden on the software of the external device.

OBJECTS OF THE INVENTION An object of the present invention is to provide a display device that can eliminate the burden of software on an external device by providing the display device with a display enlargement function.

Structure of the Invention The display device of the present invention is provided with an internal counter circuit, and controls the timing of inputting (6) display data to the internal parallel-to-serial conversion circuit and the input of display data from the parallel-to-serial conversion circuit to the shift register. By controlling the transfer timing and the shift timing of the 8-indicated data in the shift register, when enlarging the display, it is possible to input conventional display data without converting the input display data to display data for enlarged display using an external device. This makes it possible to enlarge the display with just a single touch.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 shows a block diagram of a liquid crystal display device according to an embodiment of the present invention. FIG. 4 is a timing chart showing the timing of each signal in FIG. 3 when the display is enlarged twice. In FIG. 3, the parts numbered 1 to 11 are the same as those given the same numbers in FIG. 1
2 and 13 are counter circuits (1 frequency divider), and 14 is a switch. Also, in the timing chart of diagram N4, (
A) (/i shows the waveform of the first clock signal output from the timing generation circuit 1, (B) shows the data in the shift register 3, and (Q shows the waveform of the second clock signal output from the counter circuit 12. (D) shows the parallel waveform.
It shows the serial data output from the serial conversion circuit 2, (E) shows the waveform of the N1 strobe signal output from the counter circuit 6, and (F) shows the data transfer from the latch/driver circuit 5 to the liquid crystal panel 7. (G) shows the waveform of the second strobe signal output from the counter circuit 13.
The timing at which display data is input to the serial conversion circuit 2 is shown.

A case where the display is enlarged twice in the horizontal axis direction and a case in which the display is enlarged twice in the vertical axis direction will be described below.

First, when doubling in the horizontal axis direction, the first clock signal (FIG. 4) output from the timing generation circuit 1 is input to the counter 2. The counter 12 is a frequency divider by 1, and the first clock signal is divided by 2 to become a second clock signal as shown in FIG. 4(C).

By inputting this waveform to the clock input terminal 2a of the parallel-to-serial conversion circuit 2, the timing of the data output from the parallel-to-serial conversion circuit 2 is determined as shown in FIG.
6). Note that the parallel-to-serial converter circuit 2 and shift registers 3 and 4 used in this embodiment
is a falling 9 edge trigger type. Further, the first clock signal enters the clock input terminal 3a of the shift register 3, and the data is transmitted from the serial input terminal 3C to each pit of the shift register 3 in sequence in synchronization with the first clock signal, as shown in FIG. 4 (6). and then transferred. Therefore, data D2 from the parallel-to-serial converter circuit 2 to the shift register 3 is sent in synchronization with the waveform of FIG. 4(C) as shown in FIG. Figure (0
Since the data is shifted in synchronization with the waveform shown in Figure 4 (3), which has twice the frequency of the waveform shown in Figure 4, the same data is shifted into each pit of shift register 3, two bits at a time, as shown in Figure 4 (B). be done. That is, rlolloo in FIG. 5(A)
The data for llJ is rlloollllo in Figure 5 (B).
The data becomes ooollllJ, and the data is enlarged twice in the horizontal direction, so the display is enlarged twice in the horizontal direction.

Next, when enlarging the image twice in the vertical axis direction, input the first clock signal into the counter 6, count the number m of dots on the horizontal axis of the liquid crystal panel (9) 7, and complete the first step).
The first strobe signal (FIG. 4(E)) is outputted to the latch terminal 5a of the latch/driver circuit 5 and the clock input terminal 4a of the shift register 4.
By inputting the scanning line selection signal 9. The display data 11 on the horizontal axis becomes as shown in FIG. 4(F), and dots on the selected scanning line are displayed. Here, the counter 13 counts a number 211 that is twice the number of dots on the horizontal axis of the liquid crystal panel 7.
m, and the second strobe signal (Fig. 4 (
G)) is the load terminal 2 of the parallel-serial converter circuit 2.
By inputting the display data 8 inputted from an external device into the output terminal 8b, the display data 8 inputted from the external device is parallel-transformed at the timing of the waveform shown in FIG. 4(G).
Input to serial conversion circuit 2. In other words, Fig. 4 (6
) The display data 8 is input to the parallel/serial conversion circuit 2. Further, the serial output terminal 3b and serial input terminal 3C of the shift register 3 are connected by a switch 14.

First, m-pit display data 8 is input to the parallel-to-serial conversion circuit 2, and then serially input to the shift register 3 (10). When m pieces of data enter the shift register 3, the first strobe signal is outputted from the counter circuit 6 and the selected scanning line is displayed. Here, although the counter 13 counts m first clock signals, it has not counted 2m clock signals, so the second strobe signal is not output, and no display data is input to the parallel-to-serial converter circuit 2. Therefore, counter 13
Until M outputs the second strobe signal, that is, M
] Data is shifted inside the shift register 3 for m clock signals. Serial output terminal 3b of shift register 3 and serial input terminal 3c/f switch 14
Therefore, when the counter circuit 6 counts m first clock signals and outputs the next first strobe signal, the same display data as the song is output to the display data 11 on the horizontal axis of the m pit. That will happen. At this time, the counter 13 finishes counting 2m first clock signals, outputs the second strobe signal to the load terminal 2b, and the next display data is input to the parallel-to-serial converter circuit 2. In other words, as shown in FIG.
Since the data is outputted and enlarged twice in the vertical direction, the display is enlarged twice in the vertical direction.

It should be noted that the control line L1. of the switch 14. The enlargement ratio and direction of enlargement can be arbitrarily set using the control line L of the counter 12 and the control line L3 of the counter 13. In this case, the enlargement ratio can be changed by changing the frequency division ratio by the counters 12 and 13.

Further, counter circuits 12, 13 . By using all the switches 14, it is possible to expand in both the vertical and horizontal directions.

As described above, according to the above embodiment, the counter circuit 12.
13 and switch J4 are provided to control the timing of inputting display data to the parallel/serial conversion circuit 8, the timing of transferring display data from the parallel/serial conversion circuit 8 to the shift register 3, and the shift of display data in the shift register 3. By controlling the timing of
The display can be expanded both vertically and horizontally. As a result, even when enlarging the display, it is not necessary to change the display data 8 output from the external device, and the software burden on the external device can be eliminated.

Note that the examples use liquid crystals.
The present invention can be applied to devices using electroluminescence, light emitting diodes, fluorescent display tubes, etc., and can also be applied to thermal printers.

Effects of the Invention The display device of the present invention has a display magnification function itself, and can eliminate the burden of software on an external device for display magnification.

[Brief explanation of drawings]

1(a) and 1(b) are explanatory diagrams showing display enlargement, FIG. 2 is a block diagram of a conventional liquid crystal display device, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 (A ) to 0) are timing charts showing the operation timing of each part, FIGS. 5(5) and (B) are explanatory diagrams enlarged in the horizontal axis direction, and FIG.
A) and (B) are explanatory diagrams of enlargement in the vertical axis direction. (13) 1...Timing generation circuit, 2...No (Larel/serial conversion circuit, 3.4...Shift register, 5...
・Latch O driver circuit, 6... Counter circuit, 7.
...Liquid crystal panel, 12.13...Counter circuit, 14
...Switch (14) 1st stage, 2nd figure, 3rd figure, 4L input 1

Claims (1)

[Claims] shift register and
a timing generation circuit for generating a first clock signal for controlling the timing of shifting data within the first shift register; a display means; and a timing generation circuit for generating a first clock signal output from the timing generation circuit; a first counter circuit that generates a strobe signal every time the number of signal lines of the display means is counted; and a first counter circuit that generates a strobe signal every time the number of signal lines of the display means is counted; A latch-driver circuit that converts the strobe signal into a drive signal and outputs it every time the strobe signal is output from the counter circuit, and selects a specific scanning line sequentially every time the strobe signal is generated from the first counter circuit. A second shift register that supplies a signal to the display means and a first clock signal output from the timing generation circuit are frequency-divided by counting and outputted as serial data from the parallel/Φ serial conversion circuit. a second clock signal for controlling the timing of the second clock signal;
a counter circuit, wherein the division ratio of the second counter circuit is controlled by the external device. (2) a parallel-to-serial conversion circuit that converts parallel display data input from an external device into serial data; a first shift register that stores serial data output from the parallel-to-serial conversion circuit; a switch connecting a serial output terminal and a serial input terminal of a first shift register; a timing generation circuit that generates a first clock signal for controlling the timing of shifting teno data in the first shift register;
a display means; a first counter circuit that generates a first strobe signal every time the first clock signal output from the timing generation circuit is counted by the number of signal lines of the display means; and a signal of the display means. a latch driver circuit that converts parallel data output from the first shift register to a drive signal into a drive signal and outputs the drive signal each time a first strobe signal is output from the first counter circuit; a second shift register that sequentially supplies a selection signal of a particular scanning line to the display means every time a first strobe signal is generated from the first counter circuit; a second clock signal for controlling the input timing of display data from the external device to the parallel-to-serial conversion circuit by dividing the frequency by a predetermined times the number of signal lines of the display means by counting the clock signal of the display means; Step) A second counter circuit that generates an op signal and a first clock signal outputted from the timing generation circuit are frequency-divided and output from the serial data of the parallel-to-serial conversion circuit. a third counter circuit that generates a second clock signal for controlling timing, and the division ratio of the second and third counter circuits and the on/off of the switch circuit are controlled by the external device. display device.