JPS62280897A - Liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an interface circuit for a liquid crystal display device, and particularly relates to an interface circuit for a CRT display device used in a personal computer, etc. The present invention relates to a liquid crystal display device having an interface circuit that can be used as a substitute for a light, thin, short, and small liquid crystal display device by utilizing the above.

[Summary of the invention]

The present invention is an interface circuit that uses interface signals of a CRT display to process display data in real time without using a storage circuit such as a RAM to store display data, and can display the data using a drive circuit similar to the conventional one. The present invention relates to a liquid crystal display device having:

[Conventional technology]

Since liquid crystal display devices have the characteristics of being thin, low voltage, and low power consumption, recently, large dot matrix panels have been put into practical use as display terminals for personal computers, word processors, and the like. Figure 5 shows
1 is a system configuration diagram of a conventional liquid crystal display device. As shown in FIG. 5, in the conventional liquid crystal display device, display data and simultaneous signals are input to a controller 71, which generates a timing interface signal for liquid crystal, outputs to Y-axis and X-axis drive circuits, and inputs The displayed display data is stored in the storage circuit 72 once, and then the data is sent to the X-axis drive circuit in synchronization with the liquid crystal timing interface signal. Therefore, the controller is externally connected as a circuit, tα circuit RA.
M is required for one frame capacity, and the timing generation circuit for writing, reading, etc. becomes complicated. 640 x 4
For a display device with a display capacity of 0.00 dots, if display data is transferred in parallel (4 vias) to the drive circuit, approximately 4.
0M) IZ transfer lock is required, a drive circuit with high transfer speed is required, and consumption? The T flow was also large.

[Problems to be Solved by the Invention] As described above, the conventional interface circuit eliminates the need for a memory circuit RAM as a circuit external to the controller, and converts human-generated display data into LCD interface data in real time. output to the drive circuit as

Another object of the present invention is to provide a liquid crystal display device that can tolerate a slow transfer speed by transferring data using 8-bit parallel signals.

〔Example〕

Next, one embodiment of the present invention will be described.

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a timing diagram for supplementary explanation of the circuit operation of FIG. 1.

In FIG. 1, 1Isyc is a horizontal synchronization signal, Vsyc
is a vertical synchronization signal, CK is a dot clock signal, and D is serial display data. These Hsyc, Vsyc
.

CK and D are equivalent to interface signals to a CRT display device. 1 is dot clock CK
X-axis display position adjustment circuit that counts and adjusts the display 6N area (or position) in the X-axis direction, 7 is the horizontal synchronization signal +1s
Y-axis display position adjustment circuits 4 and 5 for counting yc and adjusting the display area (or position) in the Y-axis direction are 178 and 1/8 for counting the effective dot clock φ2.
10 is a variable pull counter that sets the count value of the output φ of the AND circuit 8 to 200 or 400; 11 is an S/P conversion circuit that converts serial display data to parallel display data; 14 is a A latch circuit 17.18 temporarily stores the parallel display data output of the S/P conversion circuit 11, and a latch circuit 17.18 classifies the 8-bit output data of the latch circuit 14 into odd and even bits, and displays the data on the x-axis of the liquid crystal display device. Display data UD, to UD4. on the upper and lower electrode drive circuits of the electrodes. A buffer circuit for amplifying LD, ~LDa, and SK are for the parallel display data UD.
, -UD, , LD, -LD to a 4-bit parallel shift register circuit built in the X-axis electrode drive circuit. LK sends parallel display data U to the latch circuit built in the X@electrode drive circuit.
Latch signal for latching D + ~UD,, LDI ~LD4. FRM is scanning start data for starting scanning of the Y electrode of the liquid crystal display panel.

M is an AC driving signal for AC driving the liquid crystal panel.

Next, the operation of the present invention will be explained.

When the horizontal synchronizing signal Hsyc is manually applied to the X and other display position adjustment circuit 1, the output Xt is reset to 1L'' as shown in (A) of the timing diagram in Figure 2, and after a predetermined period of time has elapsed. It rises to "H". This time width LW can change the display start position in the X-axis display direction by arbitrarily adjusting the counter value of the built-in dot clock CK's variable pull counter. The synchronizing signal Itsyc sets the R-S flip-flop 6, so its output T1 becomes H''. Therefore, A.N.
The output φ1 of the D circuit 2 generates a dot clock for the X-axis effective display period at the timing shown in (A).

The Y-axis display position adjustment circuit 7 also has a similar configuration, and when the vertical synchronization signal Vsyc is manually applied,
As shown in , the output YT is reset to “L”
After a predetermined time has elapsed, it rises to "H". For this period width LW2, the display start position in the Y-axis direction can be adjusted by arbitrarily adjusting the built-in harriable count value.

Further, the vertical synchronizing signal νsyc sets the R-S flip-flop 9, so its output T2 becomes "H".

Therefore, the output of the AND circuit 8 is φ of the horizontal synchronizing signal Hsyc during the Y-axis effective display period at the timing shown in (B).
, outputs. Barrier pull counter] 0 is Swift 3
When 4 is ON, the count value is 200° When it is OFF, the count value is 400 ``i? Outputs the carry signal φ6.R-
Output T of S flip-flop 9! is “H”, AN
The D circuit 3 generates a dot clock φ2 during the effective display period. This dot clock φ2 is manually inputted as a shift clock for the S/P conversion circuit 11 constituted by an 8-bit shift register.

Therefore, the serial data of the display data D is converted into parallel data and output to the launch circuit 14. The dot clock φ2 during the effective display period is frequency-divided by 1/8 by the 178 counter to generate a carry signal φ. This carry signal φ.

becomes a latch signal of the latch circuit 14. Furthermore, the carry signal φ is input to the 1780 counter 5,
The frequency is divided by 1780 to generate a carry signal φ4, and the above-mentioned
Reset the R-S clip-flop 6.

Therefore, the output T is reset to "L" and the generation of the dot clock φ1 is stopped.

During the action display period, the output of the launch circuit 14 is output from the buffer circuits 17 and 18 to the X@electrode drive circuit. The odd bit output of the latch circuit 14 is
It is input to the buffer circuit 17 and outputs UD, ~UD,
The even bit output is input to the buffer circuit 18, and the LD,
~Output LD4. (D
) indicates the timing of the interface signal to the X-axis and Y-axis electrode drive circuits.

The shift clock SK is input to the 1/80 counter 28, and the carry signal LK whose frequency is divided by 1/80 is the
This is a launch signal that latches the output of a 4-pin parallel shift register with a built-in shaft electrode drive circuit.

The R-S flip-flop circuit 29 is a circuit that is set by Vsyc and reset by the latch signal LK, and outputs the scan start signal FRM of the Y-axis electrode at the timing shown in (D).

The 1/2 counter 30 generates a signal M by dividing the frequency of the FRM signal by 1/2, and inverts the polarity of the driving voltage applied to the liquid crystal every frame.

FIG. 3 is a diagram showing a system configuration of a liquid crystal display device showing an embodiment of the present invention. FIG. 3 shows the aforementioned interface circuit, 50 a Y-axis electrode drive circuit, 40 an X-axis electrode drive circuit for an X electrode in which the X electrode of the color liquid crystal display panel 44 is drawn upward, and 49 a drive circuit for an X electrode. The X-axis electrode drive circuit 50 for the X electrode drawn out to the bottom is the Y-axis 1! This is a scratch drive circuit. The X-axis electrode drive circuits 40 and 49 include a 4-bit parallel shift register 41, 46 and a latch circuit 42.
．． 47 and a liquid crystal driver part 43 and 48. Parallel display data UD, ~UD, and L
D + -LDa are simultaneously input to 4 bit parallel noft registers 41 and 46, shifted by soft clock SK, and latched into latch circuits 42 and 47 by launch clock LK. Launch circuit 42.4
The outputs latched at 7 are driven by liquid crystal drivers 43 and 45 according to the display data corresponding to the colored filter electrodes, respectively.

FIG. 4 shows an electrode configuration diagram of a liquid crystal panel used in one embodiment of the present invention. In FIG. 4, the odd-numbered electrodes x, , x, , xs . . . of the X-axis electrodes are upper extraction electrodes, and the even-numbered electrodes X, ,

-------- is the lower extraction electrode, and the upper and lower extraction electrodes are driven by separate X@ electrode drive circuits.

〔Effect of the invention〕

As described above, according to the present invention, display data can be processed and interfaced in real time using interface signals of a CRT display without using a memory circuit such as a RAM, which simplifies the circuit configuration and reduces costs. It is possible to achieve miniaturization and compact packaging. Furthermore, since display data can be transferred in 8-bit parallel to the upper and lower electrodes, the speed of the transfer shift clock signal can be doubled. Furthermore, since the pitch interval of the X-axis electrodes of the liquid crystal panel can be doubled, the connection between the liquid crystal panel and the X-axis electrode drive output becomes easier, which has great effects.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a system configuration diagram of a liquid crystal display device illustrating an embodiment of the present invention, FIG. 4 is an electrode configuration diagram of a liquid crystal panel, and FIG. 5 is a diagram of a conventional liquid crystal display device. FIG. 2 is a system configuration diagram of a display device. ■...X-axis display position adjustment circuit 7...Y-axis display position adjustment circuit 10...Barrier pull counter 1 [...S/P conversion circuit 14...Latch circuit 17.1 day... Bassoff circuit 40.49... 3 days and moon's groan C way-Example 1 wo-T otaku Jei;l
Meigabi 1t's System S Ri Part 3 g

Claims (1)

[Claims] In the interface circuit of a liquid crystal display device, an X-axis display position adjustment circuit inputs a dot clock signal to adjust the temporal timing with display data, and a horizontal synchronization signal is input to adjust the temporal timing with display data in the Y-axis direction. A Y-axis display position adjustment circuit that takes timing, a dot clock and horizontal synchronization signal counter circuit that counts the effective display area in the X-axis and Y-axis directions, and an S/P conversion circuit that converts serial display data into parallel signals. A liquid crystal display device, characterized in that the output of the S/P conversion circuit is drawn out above and below the X electrode of the liquid crystal display device and driven separately for driving each electrode. .