JP3338294B2 - Counter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter circuit, for example, used in a system controlled by a microcomputer integrated circuit or the like, or used in a microcomputer integrated circuit device and requiring low power consumption. Circuit.

[0002]

2. Description of the Related Art Generally, in an MCU (micro control unit) having a frequency divider, only one clock signal is supplied to a counter. FIG. 21 is a circuit diagram of a conventional compare up counter. FIG.
FIG. 22 is a timing chart when counting 1101 in binary (13 in decimal) by the counter circuit in FIG. 21.

The circuit shown in FIG. 21 is a general 4-bit up-counter circuit 70, a register 20 for holding the number to be counted, and Q outputs QA, QB, QC, Q of flip-flops 71 to 74, respectively. A comparison circuit 7 composed of an exclusive NOR gate and an AND gate for comparing the QD with the data held in the register 20 and outputting a count end signal when they match.
And 5. The up counter circuit 70
It comprises flip-flops 71 to 74 of stages. A count enable signal is supplied to a chip enable terminal CE of each of the flip-flops 71 to 74.
The reset signal is supplied to the reset terminal R, and the clock signal f is supplied to the clock terminal C.

Next, the operation of this counter circuit will be described.
First, data 1101 to be counted in the register 20
Is set. Subsequently, the reset signals reset the Q outputs of all the flip-flops to 0, supply the count enable signal to the count enable terminal CE of the flip-flop, and start counting. The clock signal f is inverted and supplied to the clock input terminal of the flip-flop 71. At the first falling of the clock signal f, the Q output QA of the flip-flop 71 changes from 0 to 1. At the next falling of the clock signal f, QA falls from 1 to 0, and QB inverts from 0 to 1.
QA rises again from 0 to 1 at the third falling of the clock signal f. At this time, QB holds 1 without being inverted. In this way, when the data of the next lower flip-flop falls from 1 to 0, the data held by that flip-flop is inverted and counts up. When the data of the flip-flop becomes 1101, the data held in the register 20 matches each bit of the flip-flop, so that the comparison circuit 75 outputs a count end signal.

FIG. 23 shows a conventional synchronous counter using a plurality of stages of T flip-flops. The configuration of this circuit will be described below. The inverted signal of the clock signal f is
It is supplied to clock terminals C of all flip-flops. The count enable signal is supplied to the count enable terminal CE of the first-stage flip-flop 90 and one input terminal of the AND gate 91, and the Q output terminal of the flip-flop 90 is connected to the other input terminal of the AND gate 91. Is done. The output terminal of the AND gate 91 is connected to the count enable terminal of the next-stage flip-flop and the input terminal of the AND gate. Such a configuration is repeated to form a counter. In this circuit, if the product of the data up to the preceding stage is 1 at the time of falling of the clock signal, the flip-flop performs an inversion operation. Therefore, this circuit also functions as a counter of 2 raised to the power of n, where n is the number of stages.

[0006]

In the conventional counter circuit, as shown in FIG. 22, the flip-flop of the lower bit repeatedly inverts many times, so that a large amount of power is consumed.
In the multi-stage synchronous counter shown in FIG. 23, since the clock signal f is supplied to all flip-flops, the capacity of the clock wiring 92 is large, and the power consumption is large because the clock is repeatedly inverted. I will.

[0007] The above problems also apply to all counters such as overflow counters and down counters. In view of the above problems, the present invention reduces the number of inversions of a clock signal input to a flip-flop and a flip-flop by using a source clock signal and a signal obtained by dividing the clock signal as a clock signal of a counter, It is an object to reduce power consumption of a counter circuit.

[0008]

In the conventional circuit shown in FIG. 21, QA is a clock signal obtained by dividing the frequency of the clock signal f by two, and QB is the same as a clock signal obtained by dividing the frequency of the clock signal f by four. That is, the flip-flop 72 has 2
This is the same as counting by the frequency-divided signal, flip-flop 73 is counted by the frequency-divided signal, and flip-flop 74 is counted by the frequency-divided clock. Therefore, when counting 12 in decimal, it is only necessary to perform 3 counts using the flip-flops 73 and 74 with the divide-by-4 signal.

That is, in order to solve the above-mentioned problem, the present invention receives an original clock signal, and outputs one or more different natural numbers by dividing the original clock signal by a natural number raised to the power of two.
A frequency divider that outputs a frequency-divided signal of each frequency, an original clock signal output by the frequency divider, and one or more frequency-divided signals are counted. A plurality of counters for outputting an end signal, a register for holding a number to be counted by each of the plurality of counters, a count enable circuit for supplying a count enable signal to the plurality of counters, a source clock signal, a frequency-divided signal, If the count end signal of the counter that counts the frequency-divided signal of the minimum frequency indicates incomplete, the counter that counts the frequency-divided signal of the minimum frequency is first input to the counter that counts the frequency-divided signal of the minimum frequency. Of the counter that counts the frequency-divided signal of the minimum frequency without supplying any clock signal to the other counters. Count end signal represents the end, 2
If the count end signal of the counter that counts the frequency-divided signal of the second lowest frequency indicates incomplete, the frequency-divided signal of the second lowest frequency is supplied to the counter that counts the frequency-divided signal of the second lowest frequency. If no clock signal is supplied to the other counters, the same operation is repeated in the same manner, and if any of the count end signals of the plurality of counters indicates the end, any clock signal is supplied to any of the plurality of counters. A control circuit that supplies a signal and outputs a count end signal.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 shows a configuration example of an MCU chip using the counter circuit of the present invention. MCU chip 1
Reference numeral 4 denotes a CPU, a peripheral circuit unit 12 controlled by the CPU 10, a counter 11 for outputting a count to the CPU 10, a frequency divider for the original clock signal f, and a peripheral circuit unit for dividing the original clock signal and the frequency-divided signal. It comprises a frequency divider 13 and a frequency divider 13 which supplies the frequency to the counter 11.
Conventionally, the frequency-divided signal has not been supplied to the counter 11, but the present embodiment is characterized in that it is newly supplied to the counter 11.

FIG. 1 schematically shows a first embodiment of the present invention. n, m, and k are natural numbers satisfying 0 <k <m <n. The frequency divider 101 receives the original clock signal f,
A frequency-divided signal f having a frequency of 1/2 ^{k of the} original clock frequency
/ 2 ^k and a general frequency divider that outputs a frequency-divided signal f / 2 ^m having a frequency of 1/2 ^m of the original clock frequency.

The lower bit counter group 104 counts the f output output from the control circuit 101. Counter 10
4 outputs a lower bit group count end signal when it finishes counting the number of lower bit data from the 0th bit to the (k-1) th bit of the n-bit data held by the register 107.

The middle bit counter group 105 counts the f / 2 ^k output output from the control circuit 101. When the counter 105 finishes counting the number to be counted consisting of middle-order bit data from the k-th bit to the (m-1) -th bit of the n-bit data held in the register 107,
Outputs the middle bit group count end signal.

The upper bit counter group 106 counts the output of f / 2 ^m output from the control circuit 101. When the counter 106 finishes counting the number to be counted, which includes upper bit data from the m-th bit to the (n-1) th bit of the n-bit data held in the register 107,
Outputs the upper bit group count end signal.

The register 107 holds n-bit data to be counted, and stores data from the 0th bit to the (k-1) th bit of the bit data and m-1 from the kth bit.
The data up to the bit and the data from the m-th bit to the (n-1) th bit are respectively counted by counters 104, 105, 1
06 are the numbers to be counted,
5, 106.

The count enable circuit 103 receives an externally supplied count enable signal and supplies the same count enable signal to the counters 104, 105, and 106.

The control circuit 102 controls the original clock signal f
A frequency-divided signal f / 2 ^k and a frequency-divided signal f / 2 ^m supplied from the frequency divider 101, an upper bit group count end signal,
The middle bit group count end signal and the lower bit group count end signal are input, and the counters 104, 10 and 10 are set according to the state of the upper, middle and lower bit group count end signals.
F output, f / 2 ^k output respectively supplied to 5, 106
It controls the f / 2 ^m output or outputs a count end signal.

The operation of this embodiment will be described below. When the count end signal of the higher-order bit counter group 106 indicates that the count has not been completed, the control circuit 102
Supplies the frequency-divided signal f / 2 ^m to the other counter 10
No clock signal is supplied to 4, 105. Therefore, only the counter 106 performs the counting operation.

When the upper bit counter held by the register 107 has finished counting the number to be counted, the upper bit counter group 106 supplies an upper bit group count end signal to the control circuit 102 to indicate the end.

Next, when the higher-order bit count end signal indicates the end and the count end signal of the middle-order bit counter group 105 indicates the end, the frequency-divided signal f / 2 ^k is supplied to the middle-order bit counter group 105. , Other counter 10
No clock signal is supplied to 4 and 106. As a result, only the counter 105 performs the counting operation.

Hereinafter, the counter 104 is repeated similarly.
When the count end signals of 105 and 106 indicate the end, the counters 104, 105, 10
6 does not supply any clock signal, and outputs a count end signal.

As described above, in this embodiment, the counting operation is sequentially performed from the upper bit counter group first, and when a certain counter is operating, the counting operation of the other counter is stopped. It is possible to reduce the number of inversions of the loop and reduce power consumption.

FIG. 3 shows an embodiment of the compare type up counter of the present invention. This embodiment is a modification of the embodiment shown in FIG. FIG. 4 shows the Q outputs QA, QB, QC and Q of the flip-flops 22 to 25 in FIG.
D, the original clock signal f, and its divide-by-4 signal f / 4
5 shows a timing chart of an upper bit match signal, a lower bit match signal, and a count end signal. F of FIG.
In the output and f / 4 output, a broken line indicates a signal input to the control circuit, and a solid line indicates a signal output from the control circuit. In the following timing charts, broken lines indicate signals having the same meaning.

First, the configuration of this counter will be described. The frequency divider 13 is a general frequency divider that receives the original clock signal f and outputs a quarter frequency signal f / 4 having a quarter of the original clock frequency.

The counter 21 has a lower counter 21a comprising two-stage T flip-flops 22 and 23, and a two-stage T flip-flop 22 and 23.
Upper counter 21 composed of flip-flops 24 and 25
b. The inverted signal of the original clock signal f output from the control circuit 29 is supplied to the clock input terminal of the flip-flop 22. The inverted signal of the Q output signal of the flip-flop 22 is supplied to the clock input terminal C of the flip-flop 23. The inverted signal of the frequency-divided signal f / 4 output from the control circuit 29 is supplied to the clock input terminal C of the flip-flop 24. Flip-flop 2
5, the clock input terminal C of the flip-flop 24
An inverted signal of the output signal is supplied.

The register 20 is a general register for holding data designating the number to be counted. The count enable circuit 28 receives a count enable signal and a divide-by-4 signal supplied from the outside and supplies the count enable signal to the chip enable terminals CE of the flip-flops 22 to 25. This circuit supplies and holds the count enable signal to the counter 21 when, for example, an external count enable signal indicates the count enable and the divide-by-4 signal falls.

The upper bit comparing circuit 26 is provided with an exclusive NOR gate 17 for inputting the Q output signal QD of the flip-flop 25 and the data of the most significant bit of the register 20, the Q output signal QC of the flip-flop 24 and the register 20.
An exclusive NOR gate 18 to which data of the second bit from the top is inputted and an AND gate 19 to which outputs of both gates are inputted. This circuit 26 compares the Q output signals QC and QD of the flip-flops 24 and 25 with the corresponding upper two bits of the register 20,
When both bits match, the upper bit match signal is set to 1
Otherwise, it is set to 0 and output to the control circuit 29.

The lower bit comparison circuit 27 has the same configuration as the upper bit comparison circuit 26,
The Q outputs QA and QB of 2 and 23 and the corresponding lower 2 bits of data in the register 20 are input, and the two are compared. If both 2 bits match, the lower bit match signal is set to 1; It is set to 0 and output to the control circuit 29.

The control circuit 29 outputs the original clock signal f,
A frequency-divided signal f / 4, an upper bit match signal, and a lower bit match signal supplied from the frequency divider 13 are input, and a counter 21 is provided according to the state of the upper and lower bit match signals.
, Or outputs a count end signal.

FIG. 5 shows a circuit example of the control circuit 29. Hereinafter, this circuit configuration will be described. The upper bit match signal is
It is supplied to one input terminal of an AND gate 31 and an AND gate 35 and supplied to one input terminal of an AND gate 34 via an inverter 32. The lower bit match signal is
The signal is supplied to the other input terminal of the AND gate 31 and supplied to the other input terminal of the AND gate 35 via the inverter 33. The original clock signal f is supplied to the AND gate 35.
Is supplied to the other input terminal. Also, the divide-by-4 signal f /
4 is supplied to the other input terminal of the AND gate 34. The output of the AND gate 31 becomes a count end signal. The output terminal of the AND gate 34 is connected to the clock input terminal of the flip-flop 24. And Gate 3
5 is connected to the clock input terminal of the flip-flop 22. Hereinafter, the output signals of the AND gates 34 and 35 will be referred to as f / 4 output signal and f output signal, respectively.

Next, the operation of this circuit will be described. FIG.
Shows a truth table of the circuit of FIG. As shown in FIG.
When the upper bit match signal is 0, the f / 4 output signal is a divide-by-4 signal, and the f output signal and the count end signal are 0. When the upper bit match signal is 1 and the lower bit match signal is 0, the f / 4 output signal and the count end signal are 0, and the f output signal is the original clock signal. When both the upper bit match signal and the lower bit match signal are 1, the f / 4 output signal and the f output signal are both 0, and the count end signal is 1.

The operation of the counter circuit shown in FIG. 3 will be described below. First, data to be counted, for example, 1101 in a binary number is written to the register 20. At this time, the counter 21 is reset and its output becomes 0000. 4
When the frequency-divided signal falls, the count enable circuit 22
Outputs a count enable signal and causes the counter 21 to start counting. When the upper two bits of the counter 21 do not match the data of the upper two bits of the register 20, the control circuit 29 does not supply the clock f to the flip-flop 22, but supplies the clock f to the flip-flop 24, as can be seen from the truth table of FIG. Provides a divide-by-4 signal. As a result, the upper counter 21b starts counting, and the lower counter 21a stops counting.

When the two-bit output of the high-order counter 21b matches the high-order two bits of the register 20, the high-order bit comparison circuit 26 sets the high-order bit match signal to 1 and outputs it. If the upper 2 bits match and the lower 2 bits do not match, the control circuit 29 sends the 4
The supply of the frequency-divided signal is stopped, the counting operation of the upper two bits of the counter 21 is stopped, and the original clock signal f is supplied to the flip-flop 22 so that the lower counter 21
The count operation of a is started.

When the two-bit output of the lower counter 21a and the lower two bits of the register 20 match, both the upper bit match signal and the lower bit match signal become 1, so that
The count end signal becomes 1, and the count ends.

As described above, in the present invention, the counter 2
Since the upper two bits of 1 are counted by the divide-by-4 signal, and the counting operation of the lower two bits is stopped during this period, the number of inversions of the flip-flop is reduced, and the power consumption can be reduced.

FIG. 7 shows an embodiment of the overflow type up counter of the present invention. The configuration of this circuit will be described below. In the following drawings, the same elements as those already described are denoted by the same reference numerals, and description thereof will be omitted.

The register 40 includes a 4-bit first register 40a for holding data indicating a count number and a 2-bit second register 40b for holding carry data. The registers 40a and 40b The held data is output to the data input terminals D of the flip-flops 22 to 25 of the counter 21 and the data input terminals D of the overflow flip-flops 46 and 47, and these data are output to the Q terminal of each flip-flop. You.

The counter 21 composed of flip-flops 22 to 25 and the count enable circuit 28
This is the same as that described in FIG. The upper bit overflow flip-flop 46 is a T flip-flop. The inverted signal of the Q output of the flip-flop 25 is input to the clock input terminal, and the output of the count enable circuit 28 is input to the chip enable terminal CE.
An upper bit overflow signal which is 1 when there is a carry of the flip-flop 25 and is 0 when there is no carry is outputted to the control circuit 29.

The lower bit overflow flip-flop 47 is a T flip-flop. The inverted signal of the Q output of the flip-flop 23 is input to the clock input terminal, the output of the count enable circuit 28 is input to the chip enable terminal CE, A lower bit overflow signal which is 1 when there is a carry of the loop 23 and 0 when there is no carry is outputted to the control circuit 29.

The control circuit 29 switches the clock supplied to the counter 21 in accordance with the output signals of the overflow flip-flops 46 and 47, or outputs a count end signal to end the count.

FIG. 8 shows the outputs QA,
A timing chart of QB, QC, QD, the original clock signal f, the divide-by-4 signal f / 4, the upper bit overflow signal, the lower bit overflow signal, and the count end signal is shown.

Hereinafter, the operation of the counter circuit according to the present invention will be described. Generally, when counting 1101 in a binary number, the overflow type up counter counts up from the two's complement 0011 of 1101, and ends counting when the overflow occurs. In the present embodiment, the counter 21 is divided into an upper counter 21b and a lower counter 21a to perform a counting operation. Therefore,
The number to be counted is divided into upper 2 bits and lower 2 bits. The complement of the upper two bits 11 is 01, and the carry by the complement is 0. The complement of the lower two bits 01 is 11, and the carry by the complement is 0. Therefore, the complement 0111 is stored in the register 40a,
b carries carry data 00. Before the start of counting, 01 is written to the upper counter 21b, 11 is written to the lower counter 21a, and upper carry 0 and lower carry 0 are written.
Are overflow flip-flops 46 and 47, respectively.
Is written to.

The count enable signal from the outside indicates the count enable, and when the divide-by-4 signal falls, the count enable circuit 28 outputs the count enable signal to the flip-flops 22 to 25, 46, and 47, and the counter 21 counts. Is started. When the output signal of the upper bit overflow flip-flop 46 is 0, the control circuit 29 supplies a 4-divided signal to the flip-flop 24, and the 2-bit output of the upper counter 21b is counted up. During this time, no clock is supplied to the flip-flop 22, and the output of the lower counter 21a holds 11.

When the upper counter 21b counts 11 in binary, the Q output QD of the flip-flop 25 falls from 1 to 0, and the upper bit overflow signal, which is the Q output of the upper bit overflow flip-flop 46, changes from 0 to 1. stand up. Since the lower bit overflow signal is 0, the control circuit 29 stops supplying the clock signal to the upper counter 21b, supplies the original clock signal f to the flip-flop 22, and
The count operation of 1a is started.

When the lower counter 21a counts 01 in binary, the lower bit overflow signal changes from 0 to 1
become. Since both overflow signals are 1,
The control circuit 29 sets the count end signal to 1 and ends the count operation.

In this embodiment as well, the upper 2 bits are first counted by the divide-by-4 signal, and the counting of the lower 2 bits is stopped during that time. Therefore, the number of inversions of the flip-flop of the counter is reduced, and low power consumption can be realized. .

FIG. 9 shows an embodiment of the down counter of the present invention. First, the configuration of the down counter of the present invention will be described. The register 40a is a general register that holds the number to be counted and sets it in the counter 51.

The down-counter 51 has a clock input terminal C connected to a T flip-flop 52 to which an inverted signal of the original clock signal f output from the control circuit 29 is supplied, and a clock input terminal C connected to the Q output terminal of the flip-flop 52. Counter 51 comprising a T flip-flop 53
a, and 4 output from the control circuit 29 to the clock input terminal C.
A T flip-flop 54 to which an inverted signal of the divided signal f / 4 is supplied, and a flip-flop 5 connected to the clock input terminal C.
4 and a higher-order counter 51b composed of a T flip-flop 55 connected to the Q output terminal of the fourth. Chip enable terminals CE of flip-flops 52 to 55
Is supplied with a count enable signal from the count enable circuit 28.

The upper bit count end determination circuit 56
The Q terminals QC and QD of the flip-flops 54 and 55 are connected to input terminals, respectively, and are formed by NOR gates that supply the output to the control circuit 29 as an upper bit count end signal. When the upper counter counts down and the output of the upper counter becomes 00, the output of the NOR gate becomes 1; otherwise, 0 is output.

The lower bit count end determination circuit 57
The Q terminals QA and QB of the flip-flops 52 and 53 are connected to input terminals, respectively, and are formed by NOR gates that supply the output to the control circuit 29 as a lower bit count end signal. When the lower count is down counted and the output of the lower counter becomes 00, the output of the NOR gate becomes 1, otherwise it is 0.

The control circuit 29 switches the clock supplied to the counter 51 in response to the upper bit count end signal and the lower bit count end signal, or outputs a count end signal to end the count.

FIG. 10 shows flip-flops 52 to 5
5 shows a timing chart of Q outputs QA to QD, an original clock signal f, a divide-by-4 signal f / 4, an upper bit count end signal, a lower bit count end signal, and a count end signal. .

Hereinafter, the operation of this circuit will be described. First, the data to be counted in the register 40a, for example, 2
1101 is input as a base number and written into the corresponding flip-flops 52 to 55. When a count enable signal is supplied from outside and the frequency-divided signal falls, the count enable circuit 28 outputs the count enable signal to the count enable terminals CE of the flip-flops 52 to 55.

When the upper bit count end signal is 0 indicating that the count is not completed, the control circuit 29 supplies a 4-divided signal to the flip-flop 54, and the upper counter 51
b performs a down-count operation. During this time, the counter 51
The clock is not supplied to the lower two bits of, and their outputs hold 01.

When QC and QD become 00, the upper bit count end signal changes from 0 to 1. Since the lower bit count end signal is 0, the control circuit 29 supplies the original clock signal f to the flip-flop 52 without supplying any clock to the flip-flop 54.

When QA and QB become 00, both the high-order bit count end signal and the low-order bit count end signal become 1, so that the control circuit 29 sets the count end signal to 1 and ends the count.

As described above, the upper two bits are first counted by the divide-by-4 signal, and the lower two bits are stopped during that period, so that the number of flip-flop inversions is reduced and low power consumption can be realized.

In the above, the embodiment in which the frequency divider is present in the MCU and the original clock signal and the four-frequency-divided signal are used in the 4-bit counter has been described. The present invention can also be applied to The power consumption can be reduced as the number of bits is increased and the frequency-divided signal having a high frequency division is used.

For example, when counting 2515 in decimal, the least significant bit conventionally repeats inversion 2515 times. However, when a divide-by-4 signal is used, the number of inversions of the least significant bit is 2515-4 × in the present invention. 628 = 3 times.

In the embodiment shown in FIG. 3, counting is started at the falling edge of the divide-by-4 signal. In this case, after the previous count is completed, a maximum of three clocks of the original clock signal must be waited until the next count is started, but the advantage of lower power consumption is greater.

In the embodiment described above, the falling edge of the divide-by-4 clock is used as the count start timing.
It is also possible to start counting regardless of the phase of the divided clock. In this case, at the start of counting, the states of the clock signals whose frequency is divided by four or less are checked, and the count number of the original clock from the latest falling point of the divided-by-4 signal to the start of counting is determined from the state of those clock signals. Thereafter, the count is added to the count to be counted held in the register, or the complement of the count is set in the counter, and the counting operation is started.

Hereinafter, in the 4-bit compare type up-counter to which the original clock signal and the divide-by-4 signal as shown in FIG.
A case where it is desired to count 13 in base will be described.

First, a method of adding the above-described count number to the data held in the register will be described. In this case, the configuration of the counter is the same as the configuration shown in FIG. 3 except that the frequency-divided signal f / 2 and the frequency-divided signal f / 4 of the frequency divider are further input.
A means for obtaining the number of original clock signals from the falling point of the frequency-divided signal to the present time, and setting the value obtained by adding the value to the data held by the register 20 to the register 20 is added. If addition is performed on the data held in the register, a carry may occur. Therefore, the number of bits of each of the register and the counter is increased by one bit. FIG.
FIG. 1 shows a timing chart when this method is used. Here, QA, QB, QC, QD, and QE are outputs of counters arranged from the lower bit side, and QA and QB are called lower bit groups, and QC, QD, and QE are called upper bit groups. QA ', QB', QC ', QD', and QE 'represent data held in the registers arranged from the low bit side.

Next, the operation of this circuit will be described. FIG.
As shown in the figure, the frequency-divided clock f / 4 immediately after the start of counting.
Is 1 and the frequency-divided clock f / 2 is 1. Therefore, the count number of the original clock f from the latest falling point of the divide-by-4 signal to the start of the clock is binary 11,
That is, it is understood that the decimal number is 3. Binary 11
Is added to the data held in the register, the data in the register becomes 10000 in binary. Subsequent operations are the same as in the embodiment of FIG.

Next, a method of taking the complement of the above-mentioned original clock number and setting it in the counter will be described. The configuration of the counter in this case is the same as the configuration shown in FIG. 3 except that a frequency-divided signal f / 2 and a frequency-divided signal f / 4 of the frequency divider are input, and the falling edge of the latest frequency-divided signal of four. A set circuit for obtaining the number of original clock signals from the time point to the present time and outputting the complement of the value to the lower counter is added. Further, the lower counter is 3 bits, and sets the data output by the set circuit to its output. A lower bit comparison circuit configured to set a lower bit match signal to 1 when the output of the lower 2 bits of the lower counter matches the lower 2 bits of the register and the most significant bit of the lower counter is 0; Has become.

Hereinafter, the operation of this counter circuit will be described. FIG. 12 shows a timing chart in a method of setting a complement to the counter. The output of the lower counter is QA, QB, QB 'from the lower bit side, and the output of the upper counter is QC, QD from the lower bit side. Immediately after the count is started, the frequency-divided signal f / 4 is 1, and the frequency-divided signal f / 2 is 1.
Is also 1, the set circuit calculates the original clock signal from the falling edge of the latest divided-by-4 signal to the start of counting.
It recognizes that it is 11 clocks in base, and its complement 01
Is set to the lower counter. This is performed during the counting operation of the upper counter,
Subsequent operations are the same as those of the embodiment described with reference to FIG.

The method of starting counting without waiting for the fall of the maximum frequency-divided clock can also be applied to an overflow counter or a down counter. Although these methods increase the number of elements in an actual circuit, using a large frequency-divided signal has the advantage that the next count can be started without waiting for the fall of the frequency-divided clock.

In the above-described embodiment, the signals supplied to the counter are the original clock signal and its four-frequency-divided signal. However, three or more clock signals can be used.

An embodiment in which three types of clock signals are counted in a compare-type up counter similar to that shown in FIG. 3 will be described below. This counter circuit includes a frequency divider, a counter, a count enable circuit, a register, a lower bit comparison circuit, a middle bit comparison circuit, and an upper bit comparison circuit.

The frequency divider receives the original clock signal f,
The 4-divided signal f / 4 and the 16-divided signal f / 16 are output to the control circuit. The counter has a 2-bit lower counter that counts the f output signal of the control circuit, and the f /
A 2-bit middle counter for counting four output signals,
It comprises a 4-bit high-order counter that counts the f / 16 output of the control circuit. The lower counter outputs QA and QB arranged from the lower bit side are lower bit groups, the middle counter outputs QC and QD arranged from the lower bit side are middle bit groups, and the upper counter outputs QE and QE are arranged from the lower bit side. Q
F, QG, and QH will be referred to as an upper bit group.

The count enable circuit receives an external count enable signal and a 16-frequency-divided signal, and outputs the count enable signal when the external count-enable signal indicates the count enable and when the 16-frequency-divided signal falls. It is supplied to the count enable terminal of the counter.

The register is an 8-bit register that holds the number to be counted. The high-order bit comparison circuit compares the high-order bit output of the counter with the high-order 4 bits of the register corresponding thereto, sets the high-order bit group coincidence signal to 1 when both match, and outputs 0 otherwise. I do.

The middle-order bit comparing circuit compares the middle-order bit group output of the counter with the middle-order two bits of the corresponding register, and when they match, sets the middle-order bit group match signal to 1 and outputs it. Otherwise, 0 is output.

The lower bit comparison circuit compares the output of the lower bit group of the counter with the lower 4 bits of the corresponding register, and when they match, sets the lower bit group match signal to 1 and outputs the signal. Outputs 0.

The control circuit inputs the original clock signal, the divide-by-4 signal, and the divide-by-16 signal, and outputs
Controls the clock signal to be supplied to the upper counter, middle counter, and lower counter according to the middle bit group match signal and the low bit group match signal, and outputs a count end signal when all the bit group match signals become 1. And terminates the counting operation.

FIG. 13 shows an example of the control circuit in this case. The upper bit group match signal is supplied to the AND gates 61 and 6
6 and 67, and to the AND gate 65 via the inverter 62. The middle bit group match signal is
The signal is input to the AND gate 61, input to the AND gate 66 via the inverter 63, and input to the AND gate 67. The lower bit group coincidence signal is input to the AND gate 61, and is input to the AND gate 67 via the inverter 64. The original clock signal f output from the frequency divider is input to an AND gate 67, and the frequency-divided signal f / 4 output from the frequency divider is input to the AND gate 66 and output from the frequency divider. The 16-divided signal f / 16 is input to the AND gate 65. The output of the AND gate 61 becomes a count end signal. AND gate 67, 6
6, 65 outputs are the original clock signal output, 4
It is supplied to the counter as a divided signal output and a 16 divided signal output.

Next, the operation of the present counter circuit will be described.
FIG. 14 shows 0010001 in binary (35 in decimal)
4 shows a timing chart when counting is performed. First, data to be counted is set in a register, and 16
When the divided clock falls, counting is started. At this time, since the upper bit group coincidence signal is 0, the frequency-divided 16 clock is supplied to the upper counter and counting is performed. At this time, no clock is supplied to the middle counter and the lower counter, and the counting is stopped. When the upper bit group coincidence signal becomes 1, the middle bit group coincidence signal is 1, so that the original clock signal is supplied only to the lower bit group and no clock signal is supplied to the other upper and middle counts. . When all bit group match signals become 1,
This control circuit sets the count end signal to 1 and outputs it.

This method can also be applied to the above-mentioned overflow counter, down counter and the like. Further, while the counters of the embodiments shown in FIGS. 3, 7 and 9 use four flip-flops, this embodiment uses two flip-flops and stores the upper two bits. After counting, the clock can be switched to count the remaining lower 2 bits. FIG.
5 shows an embodiment of the compare type up counter of the present invention. FIG. 16 shows a timing chart in FIG.

This circuit holds a frequency divider (not shown) which receives the original clock signal f and supplies a frequency-divided signal f / 4 to the control circuit, a 2-bit counter 80, and the number to be counted. 4-bit register 20 and control circuit 86
Consisting of

The counter 80 supplies an inverted signal of the clock signal output from the control circuit 86 to the clock terminal C.
The reset signal output from the control circuit 86 is the reset terminal R
Is supplied to the clock terminal C and the inverted signal of the Q output signal of the flip-flop 80a
And a T flip-flop 80b supplied with a reset signal output from the control circuit 86 to a reset terminal R.

The control circuit 86 includes a lower bit comparing section 81,
It comprises an upper bit comparing section 82, an AND gate 83, a reset signal generating section 84, and a clock signal selecting circuit section 85.

The lower bit comparing section 81 includes an exclusive NOR gate 81a to which the Q output QA of the flip-flop 80a and the data of the least significant bit of the register are input, the Q output QB of the flip-flop 80b and the lower two bits of the register. Exclusive NOR gate 81b to which eye data is input, and exclusive NOR gates 81a and 81
It comprises an AND gate 81c to which the output of b is input. The output of the AND gate 81c becomes a lower bit match signal. The comparison unit 81 outputs a lower bit match signal as 1 when the output of the counter and the lower 2 bits of the register match, and outputs 0 otherwise.

The upper bit comparing section 82 has the configuration described below. The data of the most significant bit of the register 20 is supplied to the input terminal of the OR gate 82c, and the data of the second bit from the top is supplied to the input terminal of the OR gate 82a. The Q output terminal of the flip-flop 80a is connected to the input terminal of the OR gate 82b, and the Q output terminal of the flip-flop 80b is connected to the input terminal of the OR gate 82d. OR gate 82a, 82b, 8
The other input terminals of 2c and 82d are connected to the output terminal of AND gate 82h. The output terminals of the OR gates 82a and 82b are connected to the input terminals of the exclusive NOR gate 82e, respectively, and the output terminals of the OR gates 82c and 82d are connected to the input terminals of the exclusive NOR gate 82f, respectively. Exclusive Noah Gate 82
The output terminals of e and 82f are AND gates 82g, respectively.
Is connected to the input terminal. The output of the AND gate 82g becomes the upper bit match signal. The output terminal of the AND gate 82g is connected to the input terminal of the AND gate 82h. The direct reset input is connected to the inverter gate 82
Via i, it is connected to another input terminal of the AND gate 82h. This circuit receives the upper 2 bits of the register 20 and the 2-bit Q output signal of the counter 80, outputs a lower bit match signal as 1 when they match, and is directly reset once 1 is output. Is held until 1

The AND gate 83 receives the lower bit match signal and the upper bit match signal, and outputs a count end signal. For example, the reset signal generating section 84 is configured such that the original clock signal is supplied to the clock terminal C, the upper bit match signal is supplied to the data terminal D, and the output terminal Q is connected to one input terminal of the AND gate 84c via the inverter 84b. And an AND gate 84 to which an upper bit match signal is supplied to the other input terminal
c, and an OR gate 84d whose one input terminal is supplied with a direct reset signal and whose other input terminal is connected to the output terminal of the AND gate 84c. This circuit supplies a reset signal to the counter 80 at the start of counting and at the time of input of a direct reset signal, and supplies a reset signal of a pulse corresponding to a half cycle of the original clock signal to the counter 80 at the end of higher-order bit counting.

The selector circuit 85 outputs the original clock signal f
And a frequency-divided signal f / 4 supplied from a frequency divider (not shown)
Is input, a clock signal is selected according to the upper bit match signal and the count end signal, and the clock signal is supplied to the counter. For example, when the count end signal indicates the end of the count, the ground potential is supplied. When the count end signal indicates that the count is not completed and the upper bit match signal indicates that the upper bit does not match, the divide-by-4 signal f / 4. And the end-of-count signal indicates incomplete,
If the upper bit match signal indicates a match, the original clock signal f is supplied.

The operation of this counter circuit will be described below.
First, the count number 1011 is set in the register 20. At the start of counting, the control circuit 86 supplies a reset signal of 1 to the counter 80 and outputs the counter outputs QA and Q
B is set to 0. Further, since both the upper bit match signal and the lower bit match signal are 0, the control circuit 86 outputs a divide-by-4 signal to the counter 80 to start the counting operation. When the output of the counter 80 becomes 10 in binary,
The upper bit match signal becomes 1. Since the lower bit match signal remains at 0, the control circuit 86 changes the reset signal from 0 to 1 to set the output of the counter 80 to 00, supplies the original clock signal to the counter 80, and starts the counting operation. When the output of the counter 80 becomes 11 in binary, the lower bit match signal becomes 1. When both the upper bit match signal and the lower bit match signal become 1, the control circuit 86
Changes the count end signal from 0 to 1 and does not supply any clock signal to the counter 80.

In the above-described embodiment, it is also possible to count the upper counter first and then count the lower counter, while counting the lower counter first and then count the upper counter. In this case, it is necessary to add a circuit for delaying the phase of the frequency-divided signal to the upper counter so that the frequency-divided signal supplied to the upper counter starts immediately after the last fall of the clock signal supplied to the lower counter. . FIG. 17 is a timing chart of a compare-type up-counter when counting 11 in decimal using this method. First, the lower counter counts for three clocks with the original clock signal f, and then the upper counter counts for two clocks with the frequency-divided signal f / 4 whose phase is delayed by three clocks with the original clock signal.

This method can be applied to other counter circuits. In the above embodiment, the counter is of an asynchronous type, but the present invention can be applied to a synchronous type counter.

FIG. 18 shows an embodiment of the present invention in which a counter is controlled by a count enable circuit. In the above embodiment, the operation of the counter is controlled by the control circuit.
In this embodiment, the operation of the counter is controlled by the count enable signal output from the count enable circuit.
n, m, and k are natural numbers satisfying 0 <k <m <n.

[0090] The frequency divider 111 is supplied with the master clock signal f, and the frequency-divided signal f / 2 ^k 1 of the frequency of 2 ^k min of the master clock frequency 1 2 ^m fraction of the master clock frequency Is a frequency divider that outputs a frequency-divided signal f / 2 ^m having a frequency of

The lower bit counter group 113 receives the lower bit count enable signal output from the count enable circuit 112 and counts the original clock signal f. The counter 113 outputs a lower bit group count end signal when it finishes counting the number of lower bit data from the 0th bit to the (k-1) th bit of the n-bit data held by the register 116.

The middle bit counter group 114 receives the middle bit count enable signal output from the count enable circuit 112 and counts the frequency-divided signal f / 2 ^k output from the frequency divider 111. The counter 114 outputs a middle bit group count end signal when it finishes counting the number of middle bits from the k-th bit to the (m-1) -th bit of the n-bit data held by the register 116. .

The upper bit counter group 115 receives the upper bit count enable signal output from the count enable circuit 112 and counts the frequency-divided signal f / 2 ^m output from the frequency divider 111. The counter 115 outputs an upper bit group count end signal when it finishes counting the number of upper bits from the m-th bit to the (n-1) th bit of the n-bit data held by the register 116.

The register 116 holds n-bit data to be counted, and stores the data from the 0th bit to the (k-1) th bit of the bit data and the (m-1) th bit from the kth bit.
The data up to the bit and the data from the mth bit to the (n-1) th bit are respectively counted by counters 113, 114, 1
The counters 113, 11
4, 115.

The count enable circuit 112 includes a count enable signal supplied from the outside, an original clock signal f, and a frequency-divided signal f / 2 supplied from the frequency divider 111.
^k and the frequency-divided signal f / 2 ^m , the higher-order bit group count end signal, the middle-order bit group count end signal, and the lower-order bit group count end signal are input. Accordingly, the counter 11
A count enable signal is supplied to 3, 114, and 115, or a count end signal is output.

FIG. 19 shows a circuit example of the count enable circuit used in the embodiment shown in FIG. The upper bit count end signal includes AND gates 121 and 126,
127 and via an inverter 122 to an AND gate 125. The middle bit count end signal is input to the AND gate 121,
The signal is input to the AND gate 126 via the reference numeral 23, and is input to the AND gate 127. The lower bit count end signal is input to the AND gate 121,
Is input to the AND gate 127 via the. The count enable signal is supplied to the data input terminal of the flip-flop 128, and the inverted signal of the frequency-divided signal f / 2 ^m output from the frequency divider 111 is applied to the flip-flop 128.
Clock terminal. Flip flip 128
Output terminals Q of the AND gates 125, 126, 127
Is connected to the input terminal. The output of the AND gate 121 becomes a count end signal. AND gate 125,1
Outputs 26 and 127 are a lower bit counter group 113 and a middle bit counter group 11 as an upper bit count enable signal, a middle bit count enable signal and a lower bit count enable signal, respectively.
4. It is supplied to the upper bit counter group 115.

The operation of the embodiment shown in FIG. 18 will be described below. The count enable circuit 112 sets the upper bit count enable signal to “1” when the count end signal of the upper bit counter group 115 is “0”,
The middle bit count enable signal and the lower bit count enable signal are set to “0”. As a result, only the counter 115 performs the counting operation of the frequency-divided signal f / 2 ^m , and the other counters do not perform the counting operation.

When the higher-order bit counter group 115 finishes counting the number to be counted by the upper-order bit counter held by the register 116, the higher-order bit counter count signal is set to “1” and supplied to the control circuit 102.

Next, the upper bit count end signal becomes "
When it is “1” and the middle bit count end signal is “0”, the count enable circuit 112 sets the middle bit count enable signal to “1” and sets the upper bit count enable signal and the lower bit count enable signal to “1”. 0 to ". As a result, only the counter 114 performs a counting operation of the frequency-divided signal f / 2 ^k, the other counter does not perform the counting operation.

The same operation is repeated in the same manner, and the counter 113,
When the count end signals 114 and 115 both become "1", the upper bit count end signal, the middle bit count end signal, and the lower bit count end signal are all set to "0", and the count end signal is set to "1". "

As described above, in the present embodiment, the counting operation is performed sequentially from the upper bit counter group, and when a certain counter is operating, the counting operation of the other counter is stopped. It is possible to reduce the number of inversions of the loop and reduce power consumption.

The counter used in the embodiment shown in FIG. 18 may be an up counter or a down counter, a compare type or an overflow type, a Johnson counter or a binary counter, a synchronous type or an asynchronous type. Further, the counter method and the counter circuit of each bit group counter may be the same or different.

FIG. 20 shows an embodiment in which the present invention is applied to a synchronous counter. In this embodiment, the counter having the configuration shown in FIG. 23 does not supply an inverted signal of the original clock signal f to all flip-flops.
An inverted signal of the original clock signal f is supplied to the first to third flip-flops, and an inverted signal of the divide-by-8 signal f / 8 is supplied to the fourth to eighth flip-flops. The divide-by-256 signal f is applied to the ninth or higher flip-flop.
/ 256 is supplied. These frequency-divided signals are supplied directly from the frequency divider. In the synchronous counter, the logical product of the Q output of the preceding T flip-flop and the count enable signal supplied to the preceding flip-flop is supplied to the count enable terminal of the main flip-flop. If the product of the data up to the preceding stage is 1, the flip-flop performs an inversion operation. Therefore, the same operation as in the related art can be performed even when the frequency-divided clock is used for the upper bits as shown in FIG. As described above, when the frequency-divided clock is supplied to the upper flip-flop, the number of times of charging and discharging is reduced, and the power consumption due to the wiring capacity is reduced. The counter described above is configured by a T flip-flop, but is not limited thereto.

[0104]

As described above, according to the present invention,
When the counter of the higher-order bit group is counting, the counting operation of the counter of the lower-order bit group is stopped, so that the number of operations of the flip-flops constituting the counter of the lower-order bit is reduced, and power consumption can be reduced.

Further, when the present invention is applied to a synchronous counter, the frequency of the clock supplied to the clock line can be locally reduced to reduce the number of clock inversions. Can be lowered. Furthermore, since the control circuit of the present invention is a simple circuit, chip cost hardly increases.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an MCU chip incorporating a counter circuit of the present invention.

FIG. 3 is a diagram showing a compare-type up counter of the present invention.

FIG. 4 is a diagram showing a timing chart of the counter shown in FIG. 3;

FIG. 5 is a diagram showing a circuit example of a control circuit of the present invention.

FIG. 6 is a diagram showing the operation of the control circuit of the present invention.

FIG. 7 is a diagram showing an overflow counter of the present invention.

FIG. 8 is a diagram showing a timing chart of the counter shown in FIG. 7;

FIG. 9 is a diagram showing a down counter of the present invention.

FIG. 10 is a diagram showing a timing chart of the down counter shown in FIG.

FIG. 11 is a diagram showing a timing chart.

FIG. 12 is a diagram showing a timing chart.

FIG. 13 is a diagram showing a circuit example of a control circuit of the present invention.

FIG. 14 is a diagram showing a timing chart.

FIG. 15 is a diagram showing a compare-type up counter of the present invention.

FIG. 16 is a diagram showing a timing chart of the counter shown in FIG.

FIG. 17 is a diagram showing a timing chart.

FIG. 18 is a diagram showing another embodiment of the present invention.

FIG. 19 is a diagram showing a count enable circuit shown in FIG. 18;

FIG. 20 is a diagram showing a synchronous counter of the present invention.

FIG. 21 is a diagram showing a conventional compare-type up counter.

FIG. 22 is a diagram showing a timing chart of the counter shown in FIG. 21.

FIG. 23 is a diagram showing a conventional synchronous counter.

[Explanation of symbols]

 101: frequency divider, 102: control circuit, 103: count enable circuit, 104: lower bit counter, 105: middle bit counter, 106: upper bit counter, 107: register.

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Kazuhiko Ohashi 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture In-house Toshiba Microelectronics Corporation (56) References JP-A-59-208945 (JP, A) JP-A Heisei 7-248741 (JP, A) JP-A-6-204873 (JP, A) JP-A-63-166318 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 21/00

Claims (9)

(57) [Claims] 1. An original clock signal is inputted, and different
A frequency divider that outputs a frequency-divided signal having a frequency of 1 / the natural number of 2 of the original clock signal for at least one natural number; and any one of the original clock signal and the one or more frequency-divided signals. A plurality of counters that output a count end signal when the number to be counted is counted; a register that holds the number to be counted by each of the plurality of counters; and a count enable signal to the plurality of counters. And a count enable circuit that supplies the original clock signal, the frequency-divided signal, and the count end signal of the plurality of counters to reduce the power consumption of the counter, and counts the frequency-divided signal of the minimum frequency. In the case where the count end signal of the counter which performs the counting is not completed, first, the counter which counts the frequency-divided signal of the minimum frequency is provided before the counter. The frequency division signal of the minimum frequency is supplied, no clock signal is supplied to the other counters, and the count end signal of the counter that counts the frequency division signal of the minimum frequency indicates the end, and the second lowest frequency If the count end signal of the counter that counts the frequency-divided signal indicates that the count has not been completed, the frequency-divided signal of the second lowest frequency is supplied to the counter that counts the frequency-divided signal of the second lowest frequency. No clock signal is supplied to the counters other than the above, and the same is repeated in the following. When all the count end signals of the plurality of counters indicate the end, any clock signal is supplied to any of the plurality of counters. A control circuit that does not supply a signal and outputs a count end signal. 2. An original clock signal is input, and different
Frequency dividers each outputting a frequency-divided signal having a frequency of 1 / the natural number power of 2 of the original clock signal for at least natural numbers; the original clock signal output by the frequency divider; A plurality of counters that count any of the frequency-divided signals and output a count end signal when the number to be counted is counted; a register that holds a number to be counted by each of the plurality of counters; In order to reduce the power consumption of the counter, the original clock signal, the frequency-divided signal, and the count end signal of the plurality of counters are input, and the count end signal of the counter that counts the frequency-divided signal of the minimum frequency is not ended. In the case of, first, a count enable signal is supplied to a counter that counts the frequency-divided signal of the minimum frequency to start counting. No count enable signal is supplied to the counter, and the count end signal of the counter that counts the frequency-divided signal of the minimum frequency indicates the end, and the count end signal of the counter that counts the frequency-divided signal of the second lowest frequency is not yet received. In the case of indicating the end, a count enable signal is supplied to the counter for counting the frequency-divided signal of the second lowest frequency to start counting, and the other counters are not supplied with the count enable signal. Repeatedly, when the count end signals of the plurality of counters indicate the end, a count enable circuit that does not supply any clock signal to any of the plurality of counters and outputs a count end signal. A counter circuit comprising: 3. A counter circuit for inputting an up-counter, a count number of the up-counter and a number to be counted by a counter held by the register, and outputting a count end signal when the two match. 3. The counter circuit according to claim 1, further comprising: 4. The counter receives a binary counter and an output signal of the most significant bit of the binary counter,
A carry flip-flop that outputs a signal indicating the presence or absence of a carry. 2 above
3. The counter circuit according to claim 1, wherein the counter is set in a binary counter and the carry flip-flop. 5. The counter according to claim 1, further comprising a down counter, and a determination circuit that outputs a count end signal when the down counter has counted the number to be counted by the counter held by the register. 3. The counter circuit according to claim 1, wherein: 6. At the start of counting, for all natural numbers k from 1 to the largest natural number n used for counting among the different natural numbers, the frequency is divided by a frequency of 1/2 k times of the original clock signal. From the phase of the signal, a counter that counts a frequency-divided signal having a frequency of 1 / n 2 of the original clock signal to be counted is a frequency-divided signal having a frequency of 1/2 n of the original clock signal. Means for calculating the number of original clock signals from the most recent signal change point to the start of counting, and changing the number to be counted by the counter held by the register according to the number. Item 3. The counter circuit according to item 1 or 2. 7. The means for changing the number to be counted includes adding the number of original clock signals from the most recent signal change point of the frequency-divided signal to the start of counting to the number to be counted held in the register. 7. The counter circuit according to claim 6, wherein: 8. A frequency divider that receives an original clock signal and outputs at least one frequency-divided signal having different frequencies, a counter that counts the clock signal, and counts with the original clock signal. A register that holds a count number and a count number to be counted by each of the frequency-divided signals, and the original clock signal, the frequency-divided signal, the count number of the counter, and data held in the register are input. After supplying a reset signal to the counter,
A clock signal of the lowest frequency is supplied to the counter, a counting operation is performed up to the number to be counted by the clock signal, a reset signal is sequentially supplied to the counter, and a clock signal of the next lowest frequency is supplied to the counter. And a control circuit for outputting a count end signal when the number of signals to be supplied is counted and the number to be counted for all clock signals is counted. 9. An original clock signal is input, and different
Frequency dividers each outputting a frequency-divided signal having a frequency of 1 / the natural number power of 2 of the original clock signal for at least natural numbers, and each of the frequency dividers outputs one of the original clock signal and the frequency-divided signal. A counter circuit comprising: a group of synchronous counters that receive a clock.