JPH10303738A - Counter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a counter capable of counting a high-frequency clock with a circuit small in circuit scale and small in power consumption. SOLUTION: An external setting value HDB denoting a count end value is divided into higher-order bits and lower-order bits, the higher-order bits are counted by using a counter circuit 12 small in circuit scale and small in power consumption and a comparator 13 detects matching. A clock is frequency-divided to make high frequency clock supply and supplied to the counter circuit 12. Then a shift register 14 and a multiplexer 15 are used to allow the shift register 14 operated by a high-frequency clock to shift the matching detection signal of the high-order bits by a digit number equivalent to the low-order bits to provide on output of a count end signal OUT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a counter for counting a predetermined number of clocks, and more particularly to a counter suitable for being incorporated in an integrated circuit using a high-speed clock.

[0002]

2. Description of the Related Art There is a counter which outputs a pulse when a predetermined number of clocks are inputted by using a synchronous counting circuit synchronized with a clock. Such a counter is widely used, for example, for generating a horizontal synchronization signal of a display device.

FIG. 6 is a block diagram of a general counter for counting a predetermined number of clocks. The counter 60 counts the number of clocks CLK by the counting circuit 61, and compares the count value (Q0 to Qn) of the counting circuit 61 with an external set value HDB (HDB0 to HDBn) indicating a predetermined number by the comparator 62. Then, when both values match, a count end signal OUT is output. Note that the counting circuit 61 is initialized by the reset signal RST. The comparator 62 is formed of, for example, an EX-NOR circuit, and receives input count values (Q0 to Qn).
And the external setting value HDB (HDB0 to HDBn) are composed of the same number of bits.

Generally, a circuit shown in FIG. 7 is used as the counting circuit 61. The counting circuit 70 outputs the clock signal C
D-type flip-flops 700 to 70n, which are output circuits to which LK is commonly input, and a feedback unit 71 that carries the count value. The count value is represented by a BCD code, where Q0 is the LSB and Qn is the MSB. By the way, the operating frequency of this circuit mainly depends on the operating speed of the feedback unit 71. That is, the feedback unit 71 is connected to the inverter 7
10, the maximum operable frequency of the counting circuit 70 is determined by the feedback unit 7 because it is constituted by gate circuits such as EX-OR circuits 720 to 72n and AND circuits 730 to 73n.
1 depends on the gate delay of the gate circuit.

In recent years, high-speed operation has been demanded for integrated circuits, and the frequency of clock signals used in the integrated circuits has been increased accordingly. However, the counting circuit 7
When the frequency of the clock signal CLK is high, the carry of the count value does not coincide with the input of the clock signal CLK due to the gate delay of the feedback unit 71, and a malfunction may occur.
Therefore, recently, without using a counting circuit as shown in FIG.
The counter is constituted only by the shift register and the flip-flop, thereby speeding up the counting operation. However,
These counting circuits have problems in circuit scale and power consumption.

Hereinafter, an example of a high-speed counting circuit applied as the counting circuit 61 in FIG. 6 will be described.

FIG. 8 shows a counting circuit described in Japanese Patent Application Laid-Open No. 63-107317. The counting circuit 80 forms an n-ary counter by connecting n flip-flops 800 to 80n in series to form a shift register. In the operating state, “1” (active level H) is input as data signal D, and in response to the input of clock signal CLK, AND circuit 811
812... The pulses O0 to On are sequentially output from the OR circuit 81n. The output Qn of the flip-flop 80n
Becomes "1", all the flip-flops 800 to 80n are initialized by the inverted output / Q.

FIG. 9 shows a counting circuit described in Japanese Patent Application Laid-Open No. Hei 5-136691. The counting circuit 90 includes a D-type flip-flop 9 to which the clock signal CLK is commonly input.
00 to 902 and T-type flip-flops 911 to 914 forming a feedback unit. However, the feedback section does not carry over as in the feedback section 71 of FIG.
That is, instead of outputting the count value of the BCD code as in the counter circuit 70 of FIG. 7, 16 different values composed of four bits Q0 to Q3 are output in response to the input of the clock signal CLK. .

[0009]

When the counting circuit shown in FIGS. 8 and 9 is used as the counting circuit 61 in FIG. 6, the following problem occurs.

For example, when a 256-ary counting circuit is considered, the counting circuit 70 of FIG. 7 is composed of eight D-type flip-flops and a corresponding feedback unit. On the other hand, the counting circuit 80 of FIG. 8 requires 256 flip-flops and gate circuits. Therefore, an increase in the circuit scale including the comparator becomes a problem. Further, since all the flip-flops operate in synchronization with a high-speed clock signal, power consumption also increases. Also, in the counting circuit 90 of FIG. 9, the number of D-type flip-flops is one less than that of the counting circuit 70 of FIG. 7, but since the feedback unit is configured by a T-type flip-flop, the feedback unit 71 of FIG. Several times the number of gates is required, which increases the circuit scale and power consumption.

Accordingly, it is an object of the present invention to provide a counter capable of counting a high-speed clock signal while suppressing an increase in circuit scale and power consumption.

[0012]

According to the present invention, a counter receives a clock signal, divides the clock signal and outputs a divided clock signal, and receives an externally set value of a predetermined number of bits. Dividing means for dividing the external set value into a first external set value having a first number of bits and a second external set value having a second number of bits; A first counting / comparing means for outputting a coincidence detection signal when a number of first external setting values are input; a second counting / comparing means operating in synchronization with the clock signal;
And a second counting and comparing means for outputting a coincidence detection signal as a counting end signal when the number of external setting values is inputted.

Preferably, the first counting and comparing means includes a first and a second flip-flop to which the frequency-divided clock signal is commonly input and a second flip-flop using the outputs of the first and second flip-flops as carry signals. And a second counting / comparing means, comprising a third and a fourth flip-flop to which a clock signal is commonly input and which outputs a coincidence detecting signal to the data. A second counting circuit including a shift register as an input is included.

Further, according to the present invention, the frequency dividing number of the frequency dividing circuit is d.
In this case, the second bit number is log ₂ d. Further, when the second bit number is 1, the number of stages of the shift register is 2 ^l −
Let it be 1.

[0015]

FIG. 1 is a block diagram of a counter according to the present invention. In the present invention, as the counting circuit 12, the counting circuit of FIG. Then, the counting circuit 12 outputs the high-speed clock signal CLK.
The clock signal CLK (hereinafter referred to as an original clock signal) input from the clock input terminal 16 is frequency-divided by the frequency dividing circuit 11 and supplied to the counting circuit 12. If the frequency-divided clock signal CLKD (hereinafter, frequency-divided clock signal) is set as the maximum operable frequency of the counter circuit 12, the counter 1
The original clock signal CLK supplied to 0 can have a frequency several times that of the divided clock signal CLKD.

In the present invention, the counting operation is performed separately for the upper bits and the lower bits. That is, assuming that the external setting value HDB representing a predetermined number is composed of n (= upper m + lower 1) bits, counting of upper m bits (0 to m−1) is performed by the counting circuit 12, and lower 1 bit The count of (0 to l-1) is performed by the shift register 14. Number of lower bits l
Is obtained by l = log ₂ d, where d is the frequency division number. The frequency division ratio is preferably a factorial of 2. For example, when the original clock signal CLK is frequency-divided by 2, l = 1, and when frequency-divided by 4, 1
In the case where the frequency is divided by 2.8 and 2.8, l = 3. At this time, the number of stages of the shift register 14 is calculated as 2 ^l -1.

The external setting value HDB is divided by the dividing means 18 ', and the upper bits HDBL + 0 to HDBM-1 are inputted to the comparator 13, and the lower bits HDB0 to HDBL-1 are inputted to the multiplexer 15. Therefore,
In the comparator 13, HDBL + of the external setting value HDB
0 to HDBM-1 (m bits) are compared with the count values Q0 to QM-1 (m bits) of the counter circuit 12, and when both values match, a match detection signal OUT0 is output from the output terminal Y. The comparator 13 is constituted by, for example, a two-input EX-NOR circuit. One input receives the output Q of the counting circuit, and the other input receives the external set value HDB. Therefore, the count values Q0 to QM-1 and the external set values HDBL + 0 to HDB
When M-1 matches, the match detection signal OUT0 becomes “1”.
(Active level H) and "0" when they do not match
(Inactive level L).

When the coincidence detection signal OUT0 is output, the signal OUT0 is shifted by the shift register 14 based on the original clock signal CLK to generate retiming coincidence detection signals OUT1 to OUT2 ^l -1. These signals OUT1 to OUT2 ^l -1 correspond to the count value of the original clock signal CLK. The generated match detection signals OUT1 to OUT1
OUT2 ^l -1 is input to the multiplexer 15, selected by the lower bit l of the external setting value HDB, and output as a counting end signal OUT. That is, the shift register 14 behaves substantially as a lower-bit counting circuit, and the multiplexer 15 substantially behaves as a lower-bit comparator.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.
The first embodiment is configured as shown in FIG. This embodiment is 8
This counter can count up to bits, that is, the original clock signal CLK from 0 to 255. In this counter 20, the original clock signal CLK is frequency-divided by 2 by the frequency-divided-by-2 circuit 11a to generate a frequency-divided clock signal CLKD. That is, the divided clock signal CLKD becomes f
In the case of [Mhz], the original clock signal CLK is 2f [Mh
z]. Since the frequency division number d is 2, the lower bit number l
Is 1, and the number of shift register stages is also 1. Therefore, the counting circuit 12a is configured to output the 7-bit count values Q1 to Q7.
7 and upper 7 bits HDB1 to HDB of external setting value HDB
7 is compared. Further, since the shift register 14a has only one stage, it is constituted by one flip-flop DF1. The flip-flop DF1 retiming the coincidence detection signal OUT0 from the comparator 13a with the original clock signal CLK and outputs the same as the coincidence detection signal OUT1. The match detection signal OUT is supplied to the multiplexer 15a.
0 and OUT1 are data input terminals DIN0 and DI
Input to N1. These match detection signals OUT0, O
UT1 is selected by the value of the lower bit HDB0 of the external setting value HDB. That is, the multiplexer 15a
Is set to the select terminal SEL, the match detection signal OUT0 is selected when the external set value HDB0 = “0”, and the match detection signal OU is set when the value is “1”.
T1 is selected and output as the count end signal OUT.

FIG. 3 shows a timing chart. In the case of the present embodiment, since the lower bit HDB0 of the external setting value is the least significant bit, the external setting value is an even number when set to "0" and an odd number when set to "1". Counting circuit 12
The output of “a” changes with an even clock of the original clock signal CLK because the divided clock signal CLKD is the divided clock signal of the original clock signal CLK. Therefore, when the match detection signal OUT0 is generated when the upper bits HDB1 to HDB7 of the external set value match, the least significant bit H
When DB0 is "0", the coincidence detection signal OUT0 becomes the counting end signal OUT in the multiplexer 15a. On the other hand, when the least significant bit HDB0 is "1", the coincidence detection signal OUT0 is adjusted to the odd clock of the original clock signal CLK by the flip-flop DF1. The coincidence detection signal OUT1 retimed in this way is used as the counting end signal O
UT. In other words, the even value match detection signal OU
T0 is shifted by one clock to provide a coincidence detection signal corresponding to an odd value.

Returning to FIG. 2, specific numerical values will be considered. For example, it is assumed that the count end signal OUT is output when the original clock signal CLK is “255”. In this case, the external setting values HDB0 to HDB7 are “11111111”.
Is set. Therefore, in the comparator 13a, the outputs Q1 to Q7 of the counting circuit 12a are "11111111 (12
7), the coincidence detection signal OUT0 is generated. Here, the counting circuit 12a outputs the frequency-divided clock CLKD
, The outputs Q1 to Q7 output "1".
27, the original clock signal CLK is "254". Now, the least significant bit HDB0 of the external setting value is “1”.
Therefore, when the 255th original clock signal CLK is generated, the coincidence detection signal OUT1 output from the flip-flop DF1 is selected by the multiplexer 15a,
The counting end signal OUT is output.

As described above, according to the present invention, even when the counting circuit 12a which does not correspond to a high frequency is used, the high-speed original clock signal C exceeding the maximum operable frequency of the counting circuit is used.
The number of LK can be counted accurately.

Next, a second embodiment of the present invention will be described. The second embodiment is configured as shown in FIG. This counter 40 is a counter capable of counting up to 8 bits as in the first embodiment.
The divided clock signal CLKD is supplied to the counting circuit 12b. Therefore, the external setting value HDB0
To HDB7 are two lower bits HDB0, HDB
1 and 6-bit upper bits HDB2 to HDB7. Further, since the shift register 14b may have three stages, the shift register 14b includes flip-flops DF1 to DF3. The match detection signals OUT1 to OUT3 output from the flip-flops DF1 to DF3 are output from the lower bits HDB0, HDB0,
The count end signal OU is selected based on the value of HDB1.
Output as T.

In the case of this embodiment, the coincidence detection signals OUT0 to OUT0
OUT3 and lower bits HDB0 and HDB of the external setting value
The correspondence with 1 is as follows. When HDB1 and HDB0 are “00”, the match detection signal O
Select UT0. When HDB1 and HDB0 are “01”, the match detection signal O
Select UT1. When HDB1 and HDB0 are "10", the match detection signal O
Select UT2. When HDB1 and HDB0 are "11", the match detection signal O
Select UT3.

FIG. 5 shows a timing chart. The counting circuit 12b according to the present embodiment operates once every four times of the original clock signal CLK.
Count up. Therefore, the four original clocks are counted by the shift register 14b to generate coincidence detection signals OUT1 to OUT3, and the multiplexer 15b compares them with the lower two bits HDB0 and HDB1 of the external set value to output the count end signal OUT.

According to the above configuration, it is possible to cope with a clock signal faster than the first embodiment. In this embodiment, the circuit scale and the power consumption of the frequency divider, the shift register and the multiplexer are slightly larger than those of the first embodiment, but the scale and the power consumption of the counting circuit and the comparison circuit are smaller. As described above, in the present invention, even if the supply clock signal is set to a high frequency, the circuit scale and power consumption do not increase so much.

[0027]

As is apparent from the above description, the counter of the present invention has a frequency divider, a shift register, and a multiplexer added to the conventional counter of FIG. , The scale of the counting circuit and the comparing circuit is reduced. Therefore, the increase in the circuit scale is small. Further, since the counting circuit can be operated at a low frequency by dividing the frequency of the original clock signal, power consumption is excellent. That is, according to the present invention, it is possible to realize a counter superior in circuit scale and power consumption to a circuit in which the counter circuit shown in FIG. 8 or 9 is applied to the counter in FIG.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the second embodiment of the present invention.

FIG. 6 is a block diagram showing a circuit configuration of a conventional counter.

FIG. 7 is a circuit diagram showing a counting circuit used in the present invention.

FIG. 8 is a circuit diagram showing a conventional high-speed counting circuit composed of a shift register.

FIG. 9 is a circuit diagram showing a conventional high-speed counting circuit constituted by flip-flops.

[Explanation of symbols]

10, 20, 40, 60 Counter 11, 11a, 11b Frequency divider 12, 12a, 12b, 61 Counting circuit 13, 13a, 13b, 62 Comparator 14, 14a, 14b Shift register 15, 15a, 15b Multiplexer 16, 17 , 18, 19 Terminal 18 'External setting value dividing means DF1-DF3 Flip-flop 700-70n, 800-80n, 900-902
D-type flip-flop 710 Inverter 720-72n EX-OR circuit 730-73n, 811,812 AND circuit 81n OR circuit 911-914 T-type flip-flop

Claims (8)

[Claims] A frequency dividing circuit for receiving a clock signal and dividing the clock signal to output a divided clock signal;
An external setting value representing a predetermined number is input and the external setting value is divided into a first external setting value represented by a first bit number and a second external setting value represented by a second bit number Dividing means, a first counting circuit for outputting a first count value represented by the first bit number in synchronization with the frequency-divided clock signal, the first external setting value and the first A first comparator that compares the count value and outputs a match detection signal when both values match, and after the clock signal is input and the match detection signal is output from the first comparator, Second
And output means for outputting the coincidence detection signal as a count end signal when the number of clock signals specified by the external setting value is input. 2. The counter according to claim 1, wherein when the frequency division number of the frequency division circuit is d, the second bit number is log ₂ d. 3. The output means includes: a second counting circuit that outputs a second count value in synchronization with the clock signal; and a second external set value to which the coincidence detection signal is input and the second external set value and the second count value. 3. The counter according to claim 1, further comprising: a second comparator that compares the count value with the second count value and outputs the match detection signal as the count end signal when the two values match. 4. The method according to claim 1, wherein the second counting circuit is a shift register that shifts the coincidence detection signal in synchronization with the clock signal and outputs the shift output as the second count value. The counter according to claim 3. 5. The counter according to claim 4, wherein when the second bit number is 1, the number of stages of the shift register is 2 ^l -1. 6. The multiplexer according to claim 1, wherein the second comparator is a multiplexer that selects the coincidence detection signal and the shift output based on the second external set value and outputs the selected signal as the count end signal. The counter according to claim 4. 7. A frequency divider for receiving a clock signal, dividing the clock signal by a factor of 2 and outputting a frequency-divided clock signal, and receiving an external set value of a predetermined number of bits and receiving the external set value With a first external setting of a first number of bits and a second
Division means for dividing the number of bits into a second external setting value, and a coincidence detection signal which operates in synchronization with the frequency-divided clock signal and receives the number of the first external setting values as the clock signal A first count comparing means for outputting the second external set value after the coincidence detection signal is output from the first count comparing means and operated in synchronization with the clock signal. A counter which outputs the coincidence detection signal as a count end signal when the counter is input. 8. The first counting / comparing means, wherein the first and second flip-flops to which the frequency-divided clock signal is commonly input and the output of the first flip-flop are used as carry signals. And a gate circuit that supplies the clock signal to the flip-flop, wherein the second count comparing means is constituted by third and fourth flip-flops to which the clock signal is commonly input, and The counter according to claim 7, further comprising a second counting circuit including a shift register that receives the coincidence detection signal as a data input.