JPS5937756A - Subcarrier msk modulator - Google Patents

Abstract

PURPOSE:To employ digital IC constitution and to perform easy and stable operation, by composing a modulator of a variable frequency divider, pseudo sine wave generating circuit which generates a staircase-wise sine wave voltage, and a D-FF. CONSTITUTION:When input data D is inputted to a D-FF11, an inversion output D based upon a 1.2kHz clock pulse is applied to the frequency divider 12. The frequency divider 12 imposes 1/2 or 1/3 frequency division on 36kHz input clock pulses C according to whether the data is at a level H or L, and outputs a 12 or 18kHz frequency division output B to the pseudo sine wave generating circuit 14 according to the state of the data D. The circuit 14 generates a one-cycle sine wave by, for example, 10 pulses, so a sine wave with 1 or 1.5 cycles is generated successively in 1/1,200sec by the 12 or 18kHz pulses. When 0 is supplied as a start signal, a D-FF13 moves the moment when data vary to the center of the sine wave by the 1.2kHz clock to start sine wave output invariably at the center.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to subcarrier MSK modulation of a data signal in data communication using a mobile phone system.

In the early days, data transmission using the FM modulation method used a method called frequency shift keying. This method modulates data by switching subcarriers from one frequency to another, but at the moment of switching, the waveform becomes discontinuous, so one frequency band widens and the cipace band is expanded. It had the disadvantage of being too wide. Therefore, in order to eliminate this drawback, a method was adopted in which subcarriers are switched using continuous waveforms. This method has advantages such as being able to narrow the baseband because there are no discontinuous points in the subcarriers, and also having good noise characteristics from the transmission line because the waveform can be analyzed and demodulated from the perspective of two phases. Data transmission using this method is called MSK. The subcarrier modulator conventionally used in MSK is one in which a clock is input to, for example, a variable frequency divider, and the output of the frequency divider is passed through a multistage filter to reduce high frequency components and output subcarriers. ing. However, such a configuration requires a multi-stage filter including an analog portion, which not only complicates the circuit but also makes it difficult to miniaturize the circuit.

Therefore, an object of the present invention is to provide a device for modulating a data signal onto subcarriers necessary for the MSK modulation method, which has two simple circuits and can be miniaturized.

According to the present invention, the frequency of the clock noculus is variably divided by the data signal, and the input signal A'.

a subcarrier for MSK modulation corresponding to the data signal; and means for synchronizing the data signal and the step-like sine wave voltage. Subcarrier MSK that generates
A modulator is obtained.

Next, a detailed explanation will be given with reference to the drawings.

FIG. 1 is a block diagram of the configuration of a conventional subcarrier MSK modulator. In Fig. 1, the 9 frequency divider 1 is the clock C.
is input and the frequency is variably divided according to the LOW level/L-(L) and HIGH level (H) of the data signal. The frequency divider output B is passed through the filter 2 and output as a subcarrier output P close to a sine wave with high frequency components reduced.

FIG. 2 is a diagram showing a time chart of the operation of the above modulator. Signals B, C, D, and P are the same as those shown in FIG. 1. As you can see from this figure 2, 1
The frequency divider output B becomes a substantially sinusoidal subcarrier output P by the filter 2.

This operation is stable and there are no particular problems with the functions.

However, as mentioned above, the filter 2 has the drawback of requiring a large configuration.

FIG. 3 is a diagram showing the configuration of an embodiment of the present invention, in which 11 is a D-flip-flop (hereinafter abbreviated as φ11) that arranges input data to 1.2 k) Iz or a multiple thereof, and 12 is a J flip-flop. - a frequency divider that is a 7-ritzo flop, 13
is the starting D-free lag flop (F/F13
), 14 is a pseudo sine wave generating circuit that generates a stepped sine wave. Before going into the explanation of this device as a whole, let us introduce the frequency divider 1.
2 and the pseudo sine wave generator 14 will be explained below. Please note the symbol B.

C and D are the same as in FIGS. 1 and 2.

However, the output Q is different from P in FIG.

FIG. 4 is a diagram showing an example of the configuration of the frequency divider 12. This frequency divider has the function of dividing the input clock signal C by V2 or 1/3 according to the level (I(,L)K) of the data D. Both 21 and 22 are flip-flops (F
A').

5 and 6 are diagrams showing voltage levels and time charts of various parts of the frequency divider of FIG. 4, respectively. The following description will be made with reference to FIGS. 4, 5, and 6. Now, a high level "H"("1" is a high level, '
0'' is a low level), S2 always outputs It H''. Therefore, since the input J1+Kl of F71;'22 becomes °H'', the output Ql(
Jz) is inverted every time the clock pulse C rises. Therefore, the clock pulse is divided by 1/2.

Next, when L'' is given to R2 as data D.

, Ql and S2 are both inverted and become "L". Furthermore, when the rise of the next (4) is S, Ql is L#gtt, S2 is inverted and becomes °'H", and when the rise of (5) is S, Ql is inverted and becomes It H" Tonashi, S2 holds H''. Although the explanation is omitted below, the output Ql is 3.
Every second rise is i<? It becomes a shape that causes russ. In other words, the frequency is divided into three.

In this way, depending on the state of R2, 1/2 of Clocknoculus
, 1/3 variable frequency division is performed.

Next, the pseudo sine wave generating circuit 14 shown in FIG. 3 will be explained. This circuit is different from a normal sine wave generation circuit because it receives a large number of pulses and generates a stepped sine wave.
For example, Japanese Patent Application Laid-Open No. 136273/1982
An example of this is shown in Publication No. 365).

Figures 7 and 8 are drawings of the general configuration of the sine wave generator (Figure 1) and the output voltage waveform diagram (Figure 3) in the above literature, with symbols omitted and changed. It is. The device shown in FIG. 7 includes a reversible counter 31 that counts clocks, a preset circuit 32 that sets an initial value,
A decoder 33 that decodes the count value 31 of the reversible counter
, an input circuit 34 for setting the maximum count value of the reversible counter 31, an output circuit 35 consisting of a voltage generation group, and a data 1 group 36 . ! :, Frizzo flop 37. FIG. 8 shows that the output voltage V of OUT changes stepwise every time a clock pulse is applied to cp of the reversible counter 31, and forms a sine wave as a whole. Note that ST is a synchronization signal input terminal for setting the data start point and the pseudo sine wave output to the median value. The details of the device shown in FIG. 7 and the operation of this device to generate the waveform shown in FIG. 8 are detailed in the above-mentioned publication, and are therefore omitted here.

Figure 9 shows that the pseudo sine wave generator shown in Figure 7 above is connected to the input CL.
Every time 10 pulses of clock pulses are added to
FIG. 4 is a diagram showing a time chart in a case where the voltage V of UT is configured to return to its original position. D, C, P, Q
are the same as the symbols in Figure 3. From Figure 3 onwards, especially the 3rd figure.
Figures 4 and 7.

The operation of the entire circuit will be explained with reference to FIG. When input data D is input to DF/F 11, 1.2 kHz
The frequency divider 12 uses the inverted output B clocked by the clock pulse C of
added to. As explained earlier, this frequency divider varies the frequency division ratio to IA and 1/3 depending on the state of R2, and the frequency divider is 12 kHz.
z (when the data is °'1") or 18kHz (when the data is "0") pulse is sent to the pseudo sine wave oscillation circuit 1.
Output to 4. Since this oscillation circuit 14 generates one cycle of sine wave with 10 pulses, 12 kf (z or 1
8 kHz pulse is 1.2 kHz or l', 8
One cycle of kHz sine wave in 1/1200 seconds and F/l
For #-, give °°0'' as the start signal.

A 1 or 2 kHz clock causes the moment when data changes to be at the center value of the sine wave output, so that the sine wave output always starts from the center value.

As can be seen from the above description, the modulator for subcarrier M8 according to the present invention can be constructed from a digital integrated circuit without using a large analog filter as in the conventional case, and can operate easily and stably. Furthermore, it is also possible to house the integrated circuits constituting the present device in a single package, allowing the device itself to be further miniaturized.

[Brief explanation of drawings]

Figure 1 is a block diagram of the configuration of a conventional subcarrier MSK modulator, Figure 2 is a diagram showing a time chart of the operation of the above modulator, and Figure 3 is a diagram showing the configuration of an embodiment of the present invention. Figure 4 is a diagram showing an example of the configuration of the frequency divider in Figure 3, Figure 5 is a diagram showing the voltage level in the frequency divider in Figure 4, and Figure 6 is the operation of the frequency divider. Figure 7 is a diagram showing the general configuration of the pseudo sine wave generation circuit in Figure 3, Figure 8 is a diagram showing the output voltage waveform of the pseudo sine wave generation circuit,
FIG. 9 is a diagram showing a time chart in the embodiment of FIG. 3. Explanation of symbols: 11 is a D-flip-flop, 12 is a frequency divider, 13 is a D-flip-flop, 14 is a pseudo sine wave generator, B is a frequency divider output, C is a clock pulse, D is data, Q is a The output is shown separately. υ Figure 1 Introduction 2 Figure 4 S, R; "Pi Figure 5" Figure 8

Claims (1)

[Claims] a frequency divider that variably divides a clock pulse according to a data signal; a pseudo sine wave generation circuit that generates a step-like sine wave voltage according to an input clock pulse; A subcarrier MSK modulation device, comprising means for synchronizing, and generating a subcarrier for MSK modulation corresponding to the data signal.