JPS6399363U - - Google Patents
Info
- Publication number
- JPS6399363U JPS6399363U JP19506886U JP19506886U JPS6399363U JP S6399363 U JPS6399363 U JP S6399363U JP 19506886 U JP19506886 U JP 19506886U JP 19506886 U JP19506886 U JP 19506886U JP S6399363 U JPS6399363 U JP S6399363U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- inverted
- measuring circuit
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の一実施例を示す構成図、第２
図は本回路の接続例を示す図、第３図、第４図は
本実施例の動作を示すタイミングチヤート、第５
図はＶＦＯＩＣのリードマージンを説明する図、
第６図は従来のこの種の測定回路の一例を示す図
である。
Ｆ／Ｆ：フリツプフロツプ、ＯＳ１〜４：ワン
シヨツト、ＡＮＤ：アンド回路、ＯＲ：オア回路
、ＳＷ１：スイツチ、ＶＲ１〜３：可変抵抗器、
ＦＤＤ：フロツピデイスク装置。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure shows a connection example of this circuit, Figures 3 and 4 are timing charts showing the operation of this embodiment, and Figure 5 shows a timing chart showing the operation of this embodiment.
The figure is a diagram explaining the lead margin of VFOIC,
FIG. 6 is a diagram showing an example of a conventional measuring circuit of this type. F/F: flip-flop, OS1-4: one shot, AND: AND circuit, OR: OR circuit, SW1: switch, VR1-3: variable resistor,
FDD: Floppy disk device.
Claims (1)
リードマージン測定回路において、前記データの
ビツト毎に反転する第一の信号の立上り毎にリト
リガーされ、その出力幅が可変である第二の信号
の反転出力によりリトリガーされる出力幅が一定
の第三の信号と、前記入力データと前記第一の信
号の反転信号とのアンド出力とをオアする如く構
成したことを特徴とするマージン測定回路。 In a read margin measuring circuit for data output from a floppy disk device, retriggering is performed at each rising edge of a first signal that is inverted for each bit of the data, and retriggering is performed by an inverted output of a second signal whose output width is variable. 1. A margin measuring circuit characterized in that the margin measuring circuit is configured to OR a third signal having a constant output width and an AND output of the input data and an inverted signal of the first signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19506886U JPS6399363U (en) | 1986-12-18 | 1986-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19506886U JPS6399363U (en) | 1986-12-18 | 1986-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6399363U true JPS6399363U (en) | 1988-06-28 |
Family
ID=31152619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19506886U Pending JPS6399363U (en) | 1986-12-18 | 1986-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6399363U (en) |
-
1986
- 1986-12-18 JP JP19506886U patent/JPS6399363U/ja active Pending
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