JPH0246204U - - Google Patents
Info
- Publication number
- JPH0246204U JPH0246204U JP12220188U JP12220188U JPH0246204U JP H0246204 U JPH0246204 U JP H0246204U JP 12220188 U JP12220188 U JP 12220188U JP 12220188 U JP12220188 U JP 12220188U JP H0246204 U JPH0246204 U JP H0246204U
- Authority
- JP
- Japan
- Prior art keywords
- output
- flop
- flip
- input data
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
- Programmable Controllers (AREA)
Description
第１図はＰＣの構成を示すブロツク図、第２図
は本考案の一実施例を示すＰＣの入力装置の回路
ブロツク図、第３図ＡおよびＢは第２図に示した
それぞれ立上がり検出回路および立下がり検出回
路の回路図、第４図および第５図は第２図に示し
た構成における各信号のタイムチヤート、第６図
はＰＣの入力装置の従来例を示すブロツク図であ
る。
３…立上がり検出回路、４…立下がり検出回路
、５…オアゲート、６，８…フリツプフロツプ、
７…アンドゲート。
Fig. 1 is a block diagram showing the configuration of a PC, Fig. 2 is a circuit block diagram of an input device of a PC showing an embodiment of the present invention, and Figs. 3 A and B are respective rise detection circuits shown in Fig. 2. 4 and 5 are time charts of each signal in the configuration shown in FIG. 2, and FIG. 6 is a block diagram showing a conventional example of an input device for a PC. 3... Rise detection circuit, 4... Fall detection circuit, 5... OR gate, 6, 8... Flip-flop,
7...and gate.
Claims (1)
がりを検出する検出回路と、 該検出回路が検出する立上がりと立下がりとの
オア出力によつてセツトされ、前記入力データの
読取りを指示する入力読取り信号でリセツトされ
る第１フリツプフロツプと、 該第１フリツプフロツプの出力と前記オア出力
とのアンド出力でセツトされる第２フリツプフロ
ツプと、 該第２フリツプフロツプの出力を、入力データ
読取りエラーを告知するための信号とする手段と を具えたことを特徴とするプログラマブルコン
トローラの入力装置。[Claims for Utility Model Registration] A detection circuit that detects rising and falling edges in a waveform of input data, and an OR output of the rising edge and falling edge detected by the detection circuit, and is set to read the input data. a first flip-flop that is reset by an input read signal indicating an error in reading input data; a second flip-flop that is reset by an AND output of the output of the first flip-flop and the OR output; An input device for a programmable controller, comprising means for generating a signal for notification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12220188U JPH0246204U (en) | 1988-09-20 | 1988-09-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12220188U JPH0246204U (en) | 1988-09-20 | 1988-09-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0246204U true JPH0246204U (en) | 1990-03-29 |
Family
ID=31369908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12220188U Pending JPH0246204U (en) | 1988-09-20 | 1988-09-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0246204U (en) |
-
1988
- 1988-09-20 JP JP12220188U patent/JPH0246204U/ja active Pending
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