JPH0186723U

JPH0186723U -

Info

Publication number: JPH0186723U
Application number: JP18275187U
Authority: JP
Priority date: 1987-11-30
Filing date: 1987-11-30
Publication date: 1989-06-08

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す構成図、第２
図はタイミングパルス発生装置の一例を示す図、
第３図は動作説明のためのタイミングチヤートで
ある。１はカウンタ、３はメモリ、４はラツチ回路、
６Ｐ及び６Ｃはノア回路、７はフリツプフロツプ
、１０Ｕは立上がり変化点の検出回路、１０Ｄは
立下がり変化点の検出回路、２１_１〜２１_８，２
２_１〜２２_８，２３_１〜２３_８，２４_１〜２４_８はイクスクルーシブノア回路、５１〜５４はアン
ド回路である。 Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure shows an example of a timing pulse generator.
FIG. 3 is a timing chart for explaining the operation. 1 is a counter, 3 is a memory, 4 is a latch circuit,
6P and 6C are NOR circuits, 7 is a flip-flop, 10U is a rising transition point detection circuit, 10D is a falling transition point detection circuit, 21 ₁ to 21 ₈ , 2
2 ₁ ~ 22 ₈ , 23 ₁ ~ 23 ₈ , 24 ₁ ~ 24 ₈ is an exclusive NOR circuit, and 51 to 54 are AND circuits.

Claims

[Claims for Utility Model Registration] A memory into which count value data at the rising and falling change points are written, a counter, and a match between the count value data at the rising change points read from the memory and the count output of the counter is detected. a second detection circuit that detects coincidence between the count value data of the falling change point read from the memory and the count output of the counter; and a detection circuit of the first and second detection circuits. A timing pulse generator comprising a flip-flop whose output controls the rise and fall of the output.