JPH02149447U - - Google Patents

Info

Publication number
JPH02149447U
JPH02149447U JP5663889U JP5663889U JPH02149447U JP H02149447 U JPH02149447 U JP H02149447U JP 5663889 U JP5663889 U JP 5663889U JP 5663889 U JP5663889 U JP 5663889U JP H02149447 U JPH02149447 U JP H02149447U
Authority
JP
Japan
Prior art keywords
output signal
cpu
circuit
resistor
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5663889U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5663889U priority Critical patent/JPH02149447U/ja
Publication of JPH02149447U publication Critical patent/JPH02149447U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案の実施例を示す回路図、第2
図は、実施例におけるタイムチヤート、第3図は
、他の実施例を示す回路図、第4図は、従来例の
フローチヤート、第5図は、他の従来例の回路図
である。 1,1a〜1e……抵抗、2……I/Oポート
、SO……出力信号、SR……リセツト信号。
Fig. 1 is a circuit diagram showing an embodiment of the present invention;
3 is a circuit diagram showing another embodiment, FIG. 4 is a flowchart of a conventional example, and FIG. 5 is a circuit diagram of another conventional example. 1, 1a to 1e...Resistor, 2...I/O port, SO...Output signal, SR...Reset signal.

Claims (1)

【実用新案登録請求の範囲】 CPUにより制御される電子機器にバージヨン
に応じて実装されるI/Oの実装/未実装を検知
する回路において、 上記I/Oの出力信号をプルアツプする抵抗と
、 上記I/Oの出力信号をラツチするとともに上
記CPUにリードされるI/Oポートとを備えた
ことを特徴とするオプシヨンハードウエア検知回
路。
[Claim for Utility Model Registration] In a circuit for detecting whether or not an I/O is mounted in an electronic device controlled by a CPU depending on the version, a resistor for pulling up an output signal of the I/O; An optional hardware detection circuit comprising an I/O port that latches the output signal of the I/O and is read by the CPU.
JP5663889U 1989-05-17 1989-05-17 Pending JPH02149447U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5663889U JPH02149447U (en) 1989-05-17 1989-05-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5663889U JPH02149447U (en) 1989-05-17 1989-05-17

Publications (1)

Publication Number Publication Date
JPH02149447U true JPH02149447U (en) 1990-12-20

Family

ID=31580641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5663889U Pending JPH02149447U (en) 1989-05-17 1989-05-17

Country Status (1)

Country Link
JP (1) JPH02149447U (en)

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