JPS6395791A - Coding device for digital image signal - Google Patents

Abstract

PURPOSE:To obtain a satisfactory reproducing image at the time of a high speed reproducing by providing the titled device with a means to distribute a block circuit, a coding circuit and variable length data and a means to execute an error correcting coding to the variable length data in which the fixed length data and the length are mutually made equal. CONSTITUTION:For example, the area of one frame formed by a digital image signal is divided into plural blocks, picture element data are coded variably in length for a block, the coding output composed of the fixed length data and the variable length data is formed and the variable length data are distributed so that the length of respective variable length data of a block can be mutually equal. An error correcting coding is executed to the variable length data in which the fixed length data and the length are equally made equal. When applied to a digital VTR, the reproducing data of the extent, in which the outline of a picture is found, can be obtained even at the time of the high speed reproducing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to encoding a digital video signal using a variable length high-efficiency code and recording the encoded digital video signal on a magnetic tape using a rotating head. The present invention relates to an applied digital image signal encoding device.

[Summary of the invention]

In this invention, an area of one frame, for example, formed by a digital image signal is divided into a large number of blocks, and pixel data is variable-length encoded for each block to form an encoded output consisting of fixed-length data and variable-length data. The variable length data is distributed so that the lengths of the variable length data in each block are equal to each other, and error correction encoding is performed on the fixed length data and the variable length data whose lengths are made equal to each other. When the present invention is applied to a digital VTR, even during high-speed playback, it is possible to obtain playback data to the extent that an outline of the screen can be understood.

[Conventional technology]

When recording a digital video signal on a magnetic tape using a rotating head, it is effective to compress the digital video signal using a high efficiency code.

Variable-length coding in which the word length (number of bits) is variable is known as one of high-efficiency codes. The applicant of this application is
As described in Japanese Patent No. 266407, a television screen is divided into a large number of blocks, and the dynamic range of each block is divided into a number of level ranges determined by a number of bits smaller than the number of original quantization bits, A high-efficiency encoding device is proposed that forms a code signal corresponding to the level range to which pixel data from which the minimum value within a block has been removed belongs. Furthermore, Japanese Patent Application No. 59-269866 proposes a highly efficient encoding device that varies the bit length of a code signal in accordance with the dynamic range.

The above-mentioned high-efficiency encoding device adapted to the dynamic range uses compression in the level direction, so compared to DPCM, subsampling, etc., problems such as error propagation and aliasing distortion do not occur during decoding, and the resulting Good transient response can be achieved. Furthermore, variable length encoding has the advantage of being able to obtain a higher compression rate without deteriorating the quality of restored images compared to fixed length encoding.

A digital video signal subjected to variable length encoding as described above is recorded as diagonal tracks on a magnetic tape by a rotating head. In addition to normal playback in which the speed of the magnetic tape is the same as that during recording, high-speed playback operation is possible in which the speed of the magnetic tape is higher than that during recording in order to quickly locate the position of a recorded image. In high-speed reproduction operations, the rotary head scans the magnetic tape across multiple tracks, so that the reproduced data is reproduced in fragments. During such high-speed reproduction, a restored image as good as that during normal reproduction operation cannot be obtained, and only a restored image that allows an outline of the reproduced image to be obtained is obtained.

The high-efficiency code adapted to the dynamic range mentioned above has the maximum value data MAX and minimum value data MIN of each block.
are each 8 bits, and in addition to this, there is a code signal corresponding to the compressed pixel data in the block having a variable number of bits. The maximum value data MAX and the minimum value data MIN are fixed length data, and the code signal is variable length data.

If the data consisting of the above-mentioned fixed length data and variable length data is recorded as diagonal tracks on a magnetic tape, if the fixed length data can be reproduced during high-speed playback operation, '
The average value data represented by A (MAX + M I N) is used as the reproduced data of the block, and although it has a mosaic shape, a reproduced image whose outline can be understood is obtained.

[Problem that the invention seeks to solve]

Block data consisting of fixed length data and variable length data has a total bit length that changes depending on the dynamic range of the block, and is recorded at non-uniform intervals on the tracks of the magnetic tape. Therefore, during high-speed playback, the fixed-length data may not be played evenly, or the bit lengths of the blocks in the playback data may not be equal, so the period at which the fixed-length data is played is not constant, and the fixed-length data cannot be played back. It becomes difficult to extract from the data, and the quality of the reproduced image during high-speed reproduction is poor. Furthermore, there were problems in that it became difficult to form a sync block by adding a synchronization signal and an address (or identification) signal to each data of a predetermined length, and that the structure of the error correction code block became complicated. .

Therefore, an object of the present invention is to make the data bit lengths of blocks composed of fixed length data and variable length data equal to each other, to facilitate the formation of a sync block or a code block of an error correction code, and to facilitate the formation of a sync block or a code block of an error correction code. An object of the present invention is to provide an encoding device that can reliably reproduce fixed-length data and obtain high-quality reproduced images.

[Means for solving problems]

In this invention, two images are formed by digital image signals.
A blocking circuit that divides a dimensional area into a plurality of blocks, an encoding circuit that performs variable length encoding on pixel data in each block to form encoded outputs of fixed length data and variable length data, and each of the blocks. means for distributing the variable length data so that the lengths of the variable length data are equal to each other, and means for performing error correction encoding on the fixed length data and the variable length data whose lengths are made equal to each other. This is an encoding device for digital image signals.

[Effect]

Since the data lengths of the blocks consisting of fixed length data and variable length data are equal, it is easy to form a sync block or an error correction code block.

Furthermore, since the fixed length data is recorded on the magnetic tape at equal intervals, the fixed length data is evenly reproduced during high speed reproduction, and a good reproduced image can be obtained.

〔Example〕

This invention will be explained in detail with reference to the drawings. This description will follow the order of the items below.

a. Configuration of the recording side, data processing C0 on the recording side, configuration of the reproduction side d. Example e of variable length code, modification a. Configuration of the recording side. ) is recorded on the magnetic tape by a rotating head. In Fig. 1, for example, l is connected to the input terminal indicated by 1.
A digital video signal whose samples are quantized to 8 bits is supplied, a horizontal synchronization signal is supplied to an input terminal designated 2, and a frame synchronization signal is supplied to an input terminal designated 3. A digital video signal is supplied to a blocking circuit 4. The blocking circuit 4 converts the input digital video signal into continuous signals for each two-dimensional block, which is a unit of encoding.

The output signal of the blocking circuit 4 is supplied to the source encoder 5. The source encoder 5 performs variable length encoding for each block. - Dynamic range adaptive coding (abbreviated as AD RC), which will be described later as an example, is applied to the source encoder 5. source encoder 5
From this, data for each block (block data) is sequentially obtained.

Block data consists of fixed length data An and variable length data B.
It is composed of n. The fixed length data An is data in which the bit length is equal between blocks, and in the case of ADRC, dynamic range data, maximum value data, or minimum value data corresponds to fixed length data. The number of quantization bits of all pixel data in one block is compressed in the source encoder 5, and for example, 8 bits are converted to 0, 1, 2, or 3.4 (bits) depending on the dynamic range of the block. A compressed code signal is obtained. Therefore, in data composed of code signals of l blocks of pixels, the via lengths are not the same between blocks.

Fixed length data An from the source encoder 5 is supplied to the multiplexer 8 via the delay circuit 6, and variable length data Bn is supplied to the multiplexer 8 via the buffer memory 7. In the buffer memory 7, the lengths of the variable length data Bn are made equal. The multiplexer 8 converts the fixed length data An and the data whose lengths are made equal to each other into one channel of data. This multiplexer 8
The output data of is supplied to the outer code encoder 9.

In this embodiment, when a digital video signal is recorded on a magnetic tape, an error-correctable code is used to prevent errors. As an error correction code, each symbol (for example, 1 byte) of data is added to the code series of both the outer code and the inner code.

8 bits) is used.

The output data of the outer code encoder 9 is sent to the shuffling circuit 1
0. The shuffling circuit 10 rearranges the order of l-frame video data and outer code parity data. This shuffling is performed to disperse burst errors such as dropouts that occur during the recording/reproducing process. Furthermore, during shuffling, the relationship that fixed length data An is generated at a constant cycle is preserved.

The output data of the shuffling circuit 10 is supplied to the inner code encoder 11, and the inner code is encoded.

Output data from the inner code encoder 11 is supplied to a sink profiling circuit 12 . A sync block is a unit of predetermined length of serial data to be recorded/reproduced, and is composed of a plurality of inner code blocks. In the sync block circuit 12, a synchronization signal and an ID signal (Rili-specific signal) are added. The ID signal includes a sync block address signal and the like. Sink block circuit 12
The recording signal from the recording signal is supplied to the channel encoder 13, and channel encoding is performed. For channel encoding, 8 is used to convert the recorded data into a preferable 9-bit pattern that reduces the DC component to zero.
-9 transformation can be used. The zero-rotation head 15, in which the output signal of the channel encoder 13 is supplied to the rotary head 15 via a recording amplifier 14 and a rotary transformer (not shown), is attached to the rotary drum, and is mounted diagonally on the circumferential surface of the rotary drum. For example, one field of recording data is recorded as one inclined track.

b. Data processing on the recording side Data processing on the recording side will be explained with reference to FIGS. 3, 4, and 5. FIG. 3A shows one frame (■, line x X pixels) of a digital video signal,
The number of quantization bits for each pixel is 8 bits. In the blocking circuit 4, one frame of data is (LO line x
XO pixels). Therefore, as shown in FIG. 3B, ((L/LO)
There is an X (X/XO) block. -For example, (
L=570. X = 720. LO=8. X0=8
), and one frame is subdivided into 5670 blocks. Data of each block is supplied to the source encoder 5 and subjected to variable length encoding. In source encoder 5,
The data of the nth block is converted into block data consisting of fixed length data An and variable length data Bn.

The variable length data consists of pixel data encoded into a smaller number of bits than the original quantization bit number (8 bits).

The variable length data in the output data of the source encoder 5 is supplied to the buffer memory 7, and as shown in FIG. 3C, the lengths of the variable length data are made equal between blocks. That is, when the encoded output of consecutive blocks n, n+Ln÷2゜n+3 is shown in Figure 3, the multiplexer 8 outputs the following for short variable length data as shown in Figure 3E. A portion of the variable length data of a block is appended, and a portion of the long variable length data is appended before the variable length data of the next block. As a result, each bronze. The length of the next block data is aligned to No bits.

FIG. 2 shows data processing performed in the buffer memory 7. One memory bank of the buffer memory 7 receives variable length data B1 . B2. ...Bn are written sequentially. n
When the writing up to the th block is completed, the reading cycle begins, and the written variable length code is sequentially read out in byte units. Fixed length data A1. A2.・
. . An is supplied to the multiplexer 8 via the delay circuit 6, and the multiplexer 8 selects the variable length data read from the buffer memory 7 after selectively outputting the fixed length data. The length of the block data (No bits) is determined in consideration of the amount of data recorded on one track of the magnetic tape. That is, the total number of bits of one field of data recorded on one track is set to a predetermined value, and the source encoder 5 always performs encoding such that this total number of bits is equal to or less than the predetermined value. conduct.

The output signal from the multiplexer 8 is divided into bytes (8 bits) as shown in FIG. 3F, and the outer code encoder 9 performs error correction encoding on each byte as one word. The fixed length data An is 2 bytes, and the length of the block data is, for example, 8 bytes. As shown in Figure 3G, the outer code is an error in which each Kl byte arranged in the horizontal direction of a matrix-like data array (JXKI) in which 8 bytes from the first block are arranged in sequence in the vertical direction is a code sequence. This is a correction code, and a 2-byte check code is generated for each series.

The data from the outer code encoder 9 and the check code of the outer code are supplied to the shuffling circuit 10. The shuffling circuit IO performs complete data shuffling for each (Jx (K1 to 2)) byte data. Figure 3H
indicates the shuffled result, and error correction encoding of the inner code is performed for every 8 consecutive bytes in the vertical direction of the shuffled data. During this shuffling, 2
Fixed length data of bytes is AI, A2゜A3 every 8 bytes
．． ..., and the relationships in which they are located in order are saved.

This 2-byte fixed-length data and 6-byte shuffled variable-length data are encoded with an inner code,
For example, a 2-byte inner code check code is added. This 8-byte data and 2-byte check code constitute an inner code block.

In the sink blocking circuit 12, as shown in FIG.
A synchronization signal and an ID signal are added to, for example, every four inner code blocks of the data from the inner code encoder 11, forming a sync plotter.

In FIG. 5, P, , Q, ~P jiff + q
, , respectively indicate check codes of inner codes. The data recorded by the synchronized plotter is transferred by the rotary head 15.
Since it is recorded on magnetic tape, fixed length data is recorded on the magnetic tape at regular intervals.

Configuration of the C0 Reproducing Side As shown in FIG. 2, the data reproduced from the magnetic tape by the rotary head 15 is transmitted through a rotary transformer (not shown), a reproducing amplifier 21. Detection circuit 2 via equalizer circuit 22
3. The detection circuit 23 shapes the reproduced signal into a pulse signal, and supplies the pulse signal to the channel decoder 24 . The channel decoder 24 decodes the channel encoding. Channel decoder 24
The output signal is supplied to the synchronization detection circuit 25.

In the synchronization detection circuit 25, the synchronization signal and the ID signal are separated, and the separated synchronization signal is supplied as a timing signal to the inner code decoder 26 and the deshuffling circuit 27.

The inner code decoder 26 decodes the inner code for each inner code block of IO bytes, that is, performs error detection and error correction using the inner code. The deshuffling circuit 27 is
It undoes the rearrangement of data performed by the shuffling circuit 10 on the recording side, and the output data of the deshuffling circuit 27 is supplied to the outer code decoder 28. The outer code decoder 28 performs error detection and error correction using the outer code for each outer code block of (K l +K 2) bytes. Error words that cannot be corrected by the inner code decoder 26 and the outer code decoder 28 are corrected in an error correction circuit provided in the outer code decoder 28.

Output data of the outer code decoder 28 is supplied to a delay circuit 29 and a buffer memory 30. The delay circuit 29 stores fixed length data and supplies the fixed length data to the source decoder 31 at the required timing.
0 is provided to convert variable length data to the original length of each block. Block data consisting of fixed length data passed through delay circuit 29 and variable length data from buffer memory 30 is supplied to source decoder 31 . In the source decoder 31, the data of each pixel with the compressed number of bits is converted into restored data with the original number of quantized bits (8 bits). In addition, the source decoder 31 includes
Fixed length data is supplied prior to variable length data, and the data length of the variable length data of that block is determined from the fixed length data. A signal indicating the data length of this variable length data is sent from the source decoder 31 to the timing control circuit 3.
2. The timing control circuit 32 supplies the delay circuit 29 and the buffer memory 30 with timing control signals necessary for outputting fixed length data and variable length data constituting one block of data.

The source decoder 31 obtains reconstructed data for (L lines x X pixels) for frame (2), and this reconstructed data is supplied to the block decomposition circuit 33 . Block decomposition circuit 3
3, the restored data of the block order is converted into data of the scanning order of the television signal. Reproduction data is taken out to the output terminal 34 of the block decomposition circuit 33.

d. Example of variable length code A variable length ADRC (dynamic range adaptive code) can be used as the variable length code.

FIG. 6 shows an ADRC encoder. The input terminal 41 in FIG. 6 is supplied with a digital video signal converted into a block order by the blocking circuit 4,
This digital video signal is supplied to a dynamic range detection circuit 42 and a delay circuit 43. The dynamic range detection circuit 42 detects the maximum value MAX and the minimum value MIN among the pixel data in the block, and calculates (MAX-
The dynamic range DR expressed as MIN=DR) is calculated. The delay circuit 43 delays the input data by the time required for the dynamic range detection circuit 42 to detect the dynamic range DR, and the output data of the delay circuit 43 is supplied to the subtraction circuit 44 .

The subtraction circuit 44 has the minimum (+!!'M I
N is supplied, and pixel data after minimum value removal is obtained from the subtraction circuit 44. Pixel data PDI after removing this minimum value
is supplied to the quantization circuit 46 via the delay circuit 45.

The quantization circuit 46 quantizes the pixel data from which the minimum value shared by the pixel data in the block has been removed, using a variable number of bits depending on the dynamic range DR of the block.

Since the video signal within a block has two-dimensional correlation and three-dimensional correlation, the dynamic range DR is small compared to the original data value, and is less than 8 bits, for example, 0 bit, 1 bit. , 2 bits, 3 bits or 4
Even when quantizing by the number of bits, quantization distortion is not noticeable.

FIG. 9 explains variable length coding. When the dynamic range DR is below the threshold (THO-1), the maximum value MAX and minimum value MIN are determined as shown in FIG. 9A.
On the receiving side, the intermediate level LO between the two is transmitted.
is considered the restoration level.

Therefore, as shown in FIG. 9A, when the dynamic range is (THO-1), the maximum distortion is EO. FIG. 9B shows a case where the dynamic range DR is (THI-1). When the dynamic range DR is less than (THI-1), the number of bits is 1 bit. Therefore, the detected dynamic range DR is divided into two level ranges, the level range to which the pixel data belongs after the minimum value of the block has been removed is checked, and one of the code signals of "0" or "1" corresponding to the level range is checked. is assigned, and the restoration level is set to LO or Ll. The maximum strain at this time is El. In the variable length coding shown in FIG. 9, the larger the dynamic range, the greater the maximum distortion (EO<El<E2<E
3<E4). Non-linear quantization is performed. Nonlinear quantization reduces the maximum distortion in blocks with a small dynamic range where quantization distortion is easily noticeable, and conversely increases the maximum distortion in blocks with a large dynamic range, thereby increasing the compression ratio.

If the dynamic range DR is (TH2-1),
As shown in FIG. 9C, the detected dynamic range DR is divided into four level ranges, and for each level range, 2 bits (00) (01) (10) (11)
are assigned, and the center level of each level range is the restoration level LO, LL.

L2. It is considered L3. Therefore, the maximum distortion is E2. Furthermore, when the dynamic range DR is less than or equal to (TH3-1), the detected dynamic range DR is divided into eight level ranges as shown in Figure 9, and 3 Bit (000) (001)
... (111) are assigned, and the center level of each level range is taken as the restoration level LO, LL...Ll. Therefore, the maximum distortion is E3.

Furthermore, when the dynamic range is T83 or more, the detected dynamic range DR is divided into 16 level ranges, and for each level range,
4 bits (0000) (0001) ... (11
11) is assigned, and the center level of each level range is set as the restoration level LO, LL...Ll5. The maximum distortion E4 when quantizing with 4 bits is determined according to the maximum dynamic range.

The quantization circuit 46 is composed of, for example, a ROM, and a data variation IQ table corresponding to the threshold values THO to TH3 is stored in this ROM.

Video data PI after minimum value removal for ROM)■
and the dynamic range DR of the block are supplied, and a load (No. 3 DT is generated) with less than the original number of quantization hits is generated, and this code No. 43 o T is output to the output terminal 4.
It is taken out at 9.

Because the amount of information generated by a series of variable-length encodings is non-uniform depending on the dynamic range, buffering is used to record video data on magnetic tape at a constant rate. For this purpose, for example, the frequency distribution of the Guinami Soi 7 range DR of all blocks within one frame is determined in the frequency aggregation circuit 47. FIG. 8 is an example of a frequency distribution summary table obtained by the frequency summary circuit 47.

In FIG. 8, the maximum dynamic range of one frame is 96. It is understood that a plurality of sets are prepared for the threshold value THO~TH3, for example, (THO~TH3).
H3L ~ (THO”TH3)++ 8 thresholds (
[A set of σ is prepared.

The frequency distribution summary table obtained by the frequency totalization circuit 47 is supplied to the threshold value determination circuit 48, and the optimal threshold value cell 1- is determined within the range where the data amount of one frame does not exceed a predetermined value N N t t (bits). is determined.

In the example shown in FIG. 8, the frequency of occurrence within one frame corresponding to the dynamic range DR is expressed as yDll.

The set of thresholds (THO−TH3) is (THO=0
．． TH1=3. TH2=11, TH3=39), the total number of bits NrI of the code signal DT generated in one frame is Nt+=(L"Vz)+
2 (y3+y4+ys ・”・+y+o )+3 (
yth+y+z+y+r ++4y111) +4 (
V3q+yao+y4I...+y116) When the total number of bits Ntl is less than the reference value Ntt, this threshold set is adopted, and when it is greater than or equal to Nft, the next threshold value is +- c"i゛HO~
TH3)z For example, (THO=2.TH1=7°TH2=
23. TH3=63) is used. With this threshold-direct cell l-(THO-TH3)g, the total number of bits Ntz of the code signal DT generated in l frame is Nth" (yy+yd+y%+yb) +
2 (yy+y++ ...+y22)" 3
(Vz1 + shift 4 pa° + y) + 4 (ys3 + ν11
4...+y96) This total number of bits Ntz is similarly compared with the reference value Ntt.

By performing the above-described data processing, the threshold determining circuit 48 determines the threshold cell 1- with the smallest distortion within a range that does not exceed the reference value Ntt. The quantization circuit 46 is provided with eight ROMs corresponding to eight sets of threshold values, and code signals generated from the eight ROMs are supplied to the selector. A 3-bit parameter code is formed that includes the set of threshold values set by the threshold determination circuit 48, and the selector is controlled by this parameter code, and the desired code signal DT is output from the selector.
is obtained. This code signal DT is variable length data.

The framing circuit 50 is supplied with the dynamic range DR, the minimum value MIN, and the threshold THO to form fixed length data. Dynamic range DR or minimum value M
The maximum value MAX may be used as fixed length data instead of IN. Threshold 4fiTHO indicates a threshold set used on the recording side, and a parameter code may be used as fixed length data instead of THO. This threshold T
HO or parameter code only needs to be transmitted once per frame, whereas dynamic range information is transmitted block by block.

FIG. 10 shows the configuration of an ADRC decoder, in which variable length data, ie, code signal DT, is supplied to the input terminal indicated by 55, and fixed length data, ie, dynamic range DR, minimum value MIN, l, threshold THO(
or parameter code) is supplied. The fixed length data is supplied to a frame decomposition circuit 57, and the code signal DT and the dynamic range DR and threshold value THO from the frame decomposition circuit 57 are supplied to a decoding circuit 58. The decoding circuit 58 is an ADRC encoder. quantization circuit 46
Conversely, the code signal DT is converted to a restored level. The restoration level from the decoding circuit 58 is supplied to an adding circuit 59;
The minimum value MIN is added to the restoration level and the restoration data is obtained at the output terminal 60.

When the ADRC decoder is used in the source decoder 31 provided on the playback side described above, the ADRC decoder is equipped with a circuit that determines the number of bits of one block of variable length data from threshold information and dynamic range information, and this number of bits is is supplied to the timing control circuit 32. Furthermore, in high-speed playback operations, data is obtained only in fragments, so error correction of the outer code and/or inner code is not performed. Furthermore, in the fast playback operation, the playback image is restored only from fixed length data. That is, an average value of a block represented by 'A (MAX + M I N) is formed from the dynamic range information of fixed length data, and a reproduced image is restored using this average value.

e. Modification Codes other than ADRC can be used as source coding for encoding the digital video signal. For example, block average value data may be used as the fixed length data, and DPCM may be used as the variable length data.

Further, in order to increase the compression ratio, a configuration may be adopted in which source coding and subsampling are used together.

〔Effect of the invention〕

According to this invention, although variable length codes are used, fixed length data that can restore the outline of the screen can be recorded or transmitted at regular intervals. Therefore, it becomes easy to form a sync plotter and to form an error correction code, and fixed-length data is evenly reproduced during high-speed reproduction, resulting in a good reproduced image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the recording side of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the reproduction side of the embodiment of the invention, and FIGS. 3 and 4 are the block diagrams of the recording side. 5 is a route map showing the data structure of the sync plotter, FIG. 6 is a block diagram showing an example of a variable length code encoder, and FIGS. 7, 8, and 9. The figure is a route map used to explain the operation of a variable-length code encoder.
FIG. 10 is a block diagram showing an example of a variable length code decoder. Explanation of main symbols in the drawings 1: Digital video signal input terminal, 4 Niblock (IJ circuit, 5: Source encoder, 7: Buffer memory, 42: Dynamometer range detection circuit, 44
: subtraction circuit, 46: quantization circuit, 47: frequency aggregation circuit, 48: threshold value determination circuit, 49: variable length data output terminal, 51: fixed length data output terminal.

Claims (1)

[Scope of Claims] A blocking circuit that divides a two-dimensional area formed by a digital image signal into a plurality of blocks, and a blocking circuit that variable-length encodes pixel data in the block for each block, and converts fixed-length data and variable-length an encoding circuit for forming an encoded output of data; means for distributing the variable length data such that the lengths of the variable length data in each of the blocks are equal to each other; 1. An encoding device for a digital image signal, comprising means for performing error correction encoding on variable length data whose lengths are made equal to each other.