JP3902032B2 - Block transform encoded data transmission apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a transmission apparatus applied to record / reproduce encoded data of a block conversion code that compresses a data amount by dividing a digital image signal into small blocks and processing each block, for example, by a digital VTR. .
[0002]
[Prior art]
When a digital video signal is recorded on a recording medium such as a magnetic tape, the amount of information is large. Therefore, in order to achieve a transmission rate that can be recorded / reproduced, the digital video signal is compressed by high-efficiency encoding. It is normal. As high-efficiency coding, ADRC, DCT (Discrete Cosine Transform), etc., in which a digital video signal is divided into a large number of small blocks and coding processing is performed for each block, are known.
[0003]
ADRC obtains a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block as described in, for example, Japanese Patent Application Laid-Open No. 61-144899, and adapts to this dynamic range. This is high-efficiency encoding that performs encoding. DCT performs cosine transform on the pixels of a block, requantizes coefficient data obtained by the transform, and further performs variable length coding. Furthermore, an encoding method has been proposed in which the difference between the average value for each block and the average value of the pixels in the block is vector-quantized.
[0004]
The encoded output obtained by block transform encoding does not have the same importance. One type of ADRC, by way of varying the number of quantization bits adaptively to the dynamic range, the dynamic range is in error, the quantization bit number of the block can not know the receiving side. As a result, the data boundary between the block and the other block becomes unknown, and the error propagates to the other block.
[0005]
[Problems to be solved by the invention]
For example, when recording / reproducing the output of block coding with a digital VTR, an error correction code is used to protect against errors during recording / reproduction. When an error that cannot be corrected by the ability of the error correction code occurs with respect to the number of quantization bits, the number of quantization bits of the block becomes unknown, and the error propagated to the entire block . As a countermeasure, the same number of quantization bits is recorded a plurality of times, but the redundancy increases and the compression efficiency decreases.
[0007]
Accordingly, an object of the present invention is to provide a block transform encoded data transmission apparatus in which the number of quantization bits as an important word can prevent error propagation due to an error while suppressing an increase in redundancy.
[0008]
[Means for Solving the Problems]
The invention of claim 1 is a quantization means for quantizing a plurality of pixels to generate quantized data with the number of quantization bits determined for each block comprising a plurality of pixels;
Means for forming a predetermined low-order bit of a simple addition value of quantization bits of a plurality of blocks, or an average value of quantization bits;
Means for configuring a dynamic range and minimum value of a plurality of blocks, quantized data, a predetermined lower bit of a simple addition value, or an average value of the number of quantization bits as a transmission unit;
A block conversion code data transmission apparatus comprising error correction coding means for performing error correction coding on a transmission unit.
[0009]
An addition value of the number of quantization bits of variable-length encoded data for a predetermined period is inserted into the transmission data. When one is an error and the added value and the other number of quantization bits are not errors, the reception side can reproduce the correct number of quantization bits. Redundancy can be reduced compared to recording the same data multiple times.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described. FIG. 1 shows a schematic configuration of signal processing of this embodiment, that is, a digital VTR. A video signal is supplied from an input terminal indicated by 1, and one sample is digitized into, for example, 8 bits by the A / D converter 2. The output data of the A / D converter 2 is supplied to the blocking circuit 3. In this embodiment, the blocking circuit 3 divides an effective area of one frame into blocks having a size of (4 × 4) pixels, (8 × 8) pixels, and the like.
[0011]
A digital video signal subjected to scan conversion in the block order from the block forming circuit 3 is supplied to the shuffling circuit 4. In the shuffling circuit 4, for example, shuffling is performed in units of blocks. The shuffling shuffles the spatial position of the block. The output of the shuffling circuit 4 is supplied to the block encoding circuit 5. The block encoding circuit 5 compresses and encodes pixel data for each block. The shuffling circuit 4 may be provided after the block coding circuit 5.
[0012]
In this embodiment, variable length ADRC is used as block coding, and this embodiment is effective as an error countermeasure for information on the number of quantization bits in variable length ADRC.
[0013]
The variable-length ADRC further improves the efficiency of the fixed-length ADRC. The number of quantization bits is, for example, 0, 1, 2, 3 bits (0 bit means that no quantization code is transmitted). When the dynamic range DR is large, the number of quantization bits is increased. When the dynamic range DR is small, the number of quantization bits is decreased. Therefore, the number of quantization bits assigned to each block can be known from the dynamic range DR of each block. More specifically, four threshold values T1, T2, T3, and T4 are prepared. When (DR <T1), the number of quantization bits n is set to 0 (that is, the code signal is transmitted). In the case of (T1 ≦ DR <T2), (n = 1), and in the case of (T2 ≦ DR <T3), (n = 2) and (T3 ≦ DR <T4) In the case of (n = 3), in the case of (T4 ≦ DR), (n = 4).
[0014]
On the playback side, if the dynamic range DR becomes an error, the number of quantization bits assigned to the block becomes unknown, and the quantization code of each block cannot be correctly cut out. Propagation errors that spread to In order to solve this problem, in the embodiment of the present invention, an added value of the number of quantization bits of a quantization code included in one sync block, for example, is transmitted for a predetermined period.
[0015]
In the block encoding circuit 5, the dynamic range DR and the minimum value MIN of each block are detected, and the video data from which the minimum value has been removed is requantized in the quantization step. In the case of variable length ADRC, the quantization step Δ is obtained by reducing the dynamic range DR by 1/2 ⁿ corresponding to the number of quantization bits n. In this quantization step Δ, the video data from which the minimum value has been removed is divided, and a value obtained by rounding down the quotient to an integer is used as quantized data (also referred to as a bit plane). The dynamic range DR, the minimum value MIN, the number of quantization bits, and the quantized data are output data of the block coding circuit 5. A dynamic range DR, a minimum value MIN, and a quantization bit number are generated as important words in each block. As will be described later, for important words, n-block important words are collected and subjected to processing such as addition, thereby strengthening protection against errors.
[0016]
Output data of the block encoding circuit 5 is supplied to the parity generation circuit 6. The parity generation circuit 6 generates the parity of the error correction code. As the error correction code, for example, a product code that performs error correction coding in each of the horizontal direction and the vertical direction of the matrix arrangement of data can be employed. A sync (SYNC) block synchronization signal and an ID signal are added to the encoded data and parity. The recording data in which the sync blocks are continuous is supplied to the channel encoding circuit 7 and subjected to channel encoding processing for reducing the DC component.
[0017]
The output data of the channel encoding circuit 7 is converted into a bit stream, and further supplied to the rotary head H via the recording amplifier 8, and the recording data is recorded on the magnetic tape T as an oblique track. Usually, a plurality of rotating heads are used, but only one head is shown for simplicity.
[0018]
The reproduction data taken out from the magnetic tape T by the rotary head H is supplied to the channel decoding circuit 12 via the reproduction amplifier 11 and is subjected to channel coding decoding. The output data of the channel decoding circuit 12 is supplied to the error correction circuit 13, and the product code is decoded. The output data generated from the error correction circuit 13 includes an error flag indicating whether or not there is an error after error correction in addition to the reproduction data. In FIG. 1, the transmission path of the error flag is indicated by a broken line.
[0019]
The output data of the error correction circuit 13 is supplied to the important word correction circuit 14. The important word correction circuit 14 corrects an important word indicated by an error flag as an error. The output data of the important word correction circuit 14 is supplied to the block decoding circuit 15. The decoding circuit 15 performs ADRC decoding using a key word that is not in error, and for a block in which the key word is in error, the key word correcting circuit 14 performs ADRC decoding using the corrected key word. Do. The important word correction circuit 14 preferably has a function of estimating an important word when an error cannot be corrected.
[0020]
For example, in the case of variable length ADRC decoding, the block decoding circuit 15 generates a decoded value Li of each pixel when the number of bits of the quantization code is n bits. This decoded value Li is expressed by the following equation.
Li = [(DR / 2 ⁿ ) × xi + MIN + 0.5]
= [Δ × xi + MIN + 0.5]
[0021]
Here, xi is a code signal value, Δ is a quantization step, and [] is a Gaussian symbol. The block decoding circuit 15 has a configuration in which the calculation in [] in the above equation is realized by, for example, a ROM and the minimum value MIN is added.
[0022]
Decoded data of the block decoding circuit 15, that is, restored data corresponding to each pixel is supplied to the deshuffling circuit 16. This circuit 16 is complementary to the shuffling circuit 4 on the recording side, and performs processing for returning the spatial position of the block to the original position. The output data of the deshuffling circuit 16 is supplied to the block decomposition circuit 17. The block decomposition circuit 17 returns the data order from the block order to the raster scan order. The output data of the block decomposition circuit 17 is supplied to the error correction circuit 18. The error correction circuit 18 interpolates data that is an error in pixel units with surrounding pixel data.
[0023]
As the interpolation process, a process in which a spatial interpolation circuit and a temporal interpolation circuit are sequentially connected can be used. The spatial interpolation circuit refers to the error flag, and interpolates this error pixel with surrounding pixels when the target pixel to be interpolated is an error. Specifically, by looking at the error flags of the surrounding 8 points (upper and lower, 4 points on the left and right and 4 points on the diagonal), first the horizontal interpolation, then the vertical interpolation, and then the diagonal direction Interpolation is performed in the priority order of interpolation, and finally replacement by simply replacing the adjacent pixels. When interpolation is performed, the error flag is reset. Pixel data that could not be interpolated by this spatial interpolation circuit is interpolated by this time direction interpolation circuit. The time direction interpolation circuit replaces the error pixel with the pixel data of the previous frame in the same spatial position as the error pixel. The output data of the error correction circuit 18 is supplied to the D / A converter 19, and the restoration data of the raster scanning order corresponding to each pixel is obtained at the output terminal 20.
[0024]
FIG. 2 shows a data structure of an embodiment in which the added value N-SUM of the number of quantization bits is recorded. FIG. 2 shows an example of the data structure of the sync block. In FIG. 2, five sync blocks recorded on one track are shown superimposed in the vertical direction. A block synchronization signal and an ID signal are added to the head of each sync block, and the parity of the inner code of the product code is added to the end of each sync block, but these are not shown.
[0025]
Each sync block stores encoded data of four ADRC blocks. For example, the first sync block includes the addition values N-SUM of the key words DR1 to DR4 and MIN1 to MIN4 of the encoded output of four ADRC blocks and the number of quantization bits of the quantization code in the first sync block. And quantization codes BP1 to BP4 are stored. If the number of quantization bits of BP1 to BP4 is BA1 to BA4,
N-SUM = BA1 + BA2 + BA3 + BA4 (1)
It is.
[0026]
Since the maximum value of the number of quantization bits is 4 bits, the maximum value of the addition value N-SUM is 16 in 4 blocks. This can be expressed by 4 bits, but 1 byte is allocated to N-SUM in the data structure. The first 9 bytes of each sync block are a fixed length data area. Four blocks of quantized data BPi to BPi + 3 are arranged in the remaining l-length area of the data area of each sync block. Therefore, the length of the data area of one sync block is (9 + 1) bytes. The data amount of the first to fifth sync blocks is 5 × (9 + 1) bytes.
[0027]
By recording the added value N-SUM in this way, propagation errors can be prevented. For example, when an error occurs in the dynamic range DR3 of the first sync block, conventionally, the quantization bit number BA3 of the quantization code BP3 is unknown. However, the number of quantization bits BA3 can be found on the reproduction side by the calculation of BA3 = N−SUM− (BA1 + BA2 + BA4). Thereby, the quantization code BP3 can be correctly cut out, and as a result, BP4 can also be cut out correctly. Since the dynamic range DR3 itself cannot be corrected, it is necessary to estimate the dynamic range DR3 by interpolation or the like.
[0028]
In the above example, four quantization bit numbers are added to form an added value N-SUM. When this is further expanded, if an addition value of the number of quantization bits of various patterns is stored in different sync blocks and different tracks, not only one but also more errors can be corrected. That is, if n addition values N-SUMi are stored,
Σa (i, j) × BAj = N-SUMi (i = 0 to n−1) (2)
However, Σ means addition from j = 0 to j = n−1, and a (i, j) is an addition pattern indicating which BA is added. By solving the above simultaneous equations, the number of quantization bits BAj of a plurality of errors can be corrected.
[0029]
As an example, in the data configuration of FIG. 2, it is assumed that not only the addition value of the number of quantization bits in each sync block but also the addition value of the number of quantization bits in the vertical direction of 5 sync blocks is stored. For example, if the added value N-SUMj of BA3, BA7, BA11, BA15, and BA19 is also stored, the number of quantization bits can be known even if two of DR3 and DR4 are in error. That is, first, BA3 can be corrected by BA7, BA11, BA15, BA19 and the added value N-SUMj. Next, BA4 can be corrected using BA1, BA2, and corrected BA3.
[0030]
FIG. 3 shows an example of a circuit for obtaining information on the correct number of quantization bits using the added value N-SUM. In FIG. 3, the data and error flag from the previous error correction circuit are supplied to the bit allocation determination circuit 51. The error flag is 1-bit data indicating the presence or absence of an error for each sample of the dynamic range DR, the minimum value MIN, and the quantization code. An error flag is supplied to the counter 53.
[0031]
The counter 53 counts error flags relating to the dynamic range DR and the added value N-SUM of each sync block. The count value of the counter 53 is supplied to the determination circuit 54. The determination circuit 54 refers to the count value and the error flag to generate a determination result, and this determination result is supplied to the bit allocation correction circuit 55 and the selection circuit 52. . In response to the determination result, the number of quantization bits is corrected in the bit allocation correction circuit 55, and the selection circuit 52 is controlled in accordance with the determination result. The determination result distinguishes the following three cases.
[0032]
(1) The selection circuit 52 selects the number of quantization bits obtained from the dynamic range DR by the bit allocation determination circuit 51 having the correct dynamic range DR.
(2) The correction circuit 55 in which the added value N-SUM is correct and one DRk is an error calculates the correct k-th block quantization bit number BAk as described above. The selection circuit 52 selects the corrected BAk instead of the information from the determination circuit 51, and clears the error flag of BAk.
(3) In this case where two or more N-SUM and DR are errors, correction is not possible, and the selection circuit 52 may select either of the two inputs.
[0033]
The quantization bit number information from the selection circuit 52 is supplied to the bit plane cut-out circuit 56, and the quantization code BP in the sync block is cut out with a correct delimiter. The output of this cut-out circuit 56 is supplied to the ADRC decoder 57, and the ADRC is decoded. In the case of variable length ADRC, a buffering process is performed to control the data amount of the quantized data in a predetermined period such as one track, a plurality of sync blocks, and one sync block at a predetermined period. The present invention can also be applied when this buffering process is performed.
[0034]
In order to reduce the number of bits of the added value, only the lower 8 bits of the added value may be transmitted (or recorded). Further, an exclusive OR or an average value may be used instead of the simple addition value. Also, although ADRC is used as block coding, other block coding such as DCT may be used.
[0035]
【The invention's effect】
The present invention, than are predetermined low order bits of the plurality of blocks quantization bit number and the quantized data and the simple addition value or an average value of the quantization bit number, recorded, it is possible to suppress an increase in redundancy Nagado.
[Brief description of the drawings]
FIG. 1 is a block diagram of a recording / reproducing circuit of a digital VTR to which the present invention can be applied.
FIG. 2 is a schematic diagram illustrating an example of a configuration of a sync block according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating an example of a quantization bit number correction circuit according to an embodiment of the present invention.
[Explanation of symbols]
14 ... Keyword correction circuit, 51 ... Bit assignment determination circuit, 54 ... Determination circuit, 55 ... Bit assignment correction circuit

Claims (1)

Quantization means for generating quantized data by quantizing the plurality of pixels with the number of quantization bits determined for each block composed of a plurality of pixels;
Means for forming a predetermined lower bit of a simple addition value of the number of quantization bits of the plurality of blocks, or an average value of the number of quantization bits;
Means for configuring the dynamic range and minimum value of the plurality of blocks, the quantized data and a predetermined lower bit of the simple addition value, or an average value of the number of quantization bits as a transmission unit;
A data transmission apparatus for block conversion codes, comprising: error correction encoding means for performing error correction encoding on the transmission unit.

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