JP2982232B2 - Digital image signal recording / reproducing apparatus and recording / reproducing method - Google Patents

Description

The present invention is effective for a digital image signal recording / reproducing apparatus and recording / reproducing method, particularly for preventing dubbing of video software.

[Summary of the Invention]

In the present invention, multi-stage ADRC is used during self-recording / reproduction, and high-quality recording / reproduction is enabled.At dubbing, multi-stage ADRC and non-edge matching quantization and non-edge matching are performed in response to an ID signal in input data. Is selected, and in the case of video software, non-edge matching quantization is performed.
By inserting an ID signal indicating that, dubbing of video software can be substantially prevented.

[Conventional technology]

As coding for compressing the transmission data amount of a video signal, the present applicant has proposed coding (referred to as ADRC) adapted to a dynamic range.

FIG. 7A is used for explaining the quantization of ADRC. The dynamic range DR (difference between the maximum value MAX and the minimum value MIN) is, for example, (8 lines × 8 pixels = 64 pixels) 2
It is calculated for each dimensional block. Further, the minimum level (minimum value) MIN in the block is removed from the input pixel data. The pixel data from which the minimum value has been removed is converted into a code signal. This quantization equally divides the dynamic range DR detected into four level ranges A0 to A3 corresponding to a bit number smaller than the original quantization bit number, for example, 2 bits, and a level to which each pixel data in the block belongs. This is a process of detecting a range and generating a code signal indicating the level range.

In FIG. 7A, the dynamic range DR of the block is 4
It is divided into a plurality of level ranges A0 to A3. Pixel data included in the minimum level range A0 is encoded as (00), pixel data included in the level range A1 is encoded as (01), and pixel data included in the level range A2 is encoded as (10). The pixel data included in the maximum level range A3 is encoded as (11). Therefore, the 8-bit data of each pixel is compressed to 2 bits and transmitted.

On the reception side, the received code signal is
Restored to L3. This representative level L0 to L3 is the level range
It is the middle level of each of A0 to A3. The quantization shown in FIG. 7A is called non-edge matching (NEM) quantization.

On the other hand, as shown in FIG. 7B, 1 / 6DR including the minimum value MIN
Level range A0 and 1 / 6DR level range including maximum value MAX
The quantization of ADRC in which A3 and two 1 / 3DR level ranges A1 and A2 are set is referred to as edge matching (EM) quantization.

NEM quantization has the advantage that quantization distortion can be statistically reduced. However, when applied to a digital VTR, there is a drawback that the dynamic range DR decreases every time dubbing is performed, and the degree of image quality deterioration is large. EM quantization is the minimum value MI
Since N and the maximum value MAX are saved even if dubbing is performed,
There is an advantage that the degree of image quality deterioration due to dubbing is small. However, since the width of the level ranges A1 and A2 is larger than that of NEM quantization, there is a disadvantage that quantization distortion is large.

Furthermore, the NEM quantization has a problem in that ring distortion and impulse noise cause block distortion. In order to solve this problem, the present applicant has filed Japanese Patent Application No. 61-202118.
As described in the specification, a method for performing preprocessing on input data converted into a block structure is proposed. This method is called a multi-stage ADRC. The average value MAX of the input data values included in the maximum level range (A3 in FIG. 7A) when the dynamic range is equally divided by the number of quantization bits of the ADRC. 'And the minimum level range (FIG. 7A
And the average value MIN 'of the input data contained in A0) is detected, and as shown in FIG.
And the average value MIN 'are subjected to EM quantization so as to obtain the restoration levels L3 and L0, respectively.

Multi-stage A that performs EM quantization by pre-processing with the above NEM quantization
In the DRC, even in a block including ringing, the maximum value is changed not to the peak of the ringing but to the average value MAX ', and similarly, the minimum value is changed to MIN'. Since EM quantization is performed within the modified dynamic range DR 'determined by MAX' and MIN ', the difference between the restoration level and the restoration level of an adjacent block is reduced, and the occurrence of block distortion is prevented.

Also, since the multi-stage ADRC has restoration levels including MAX 'and MIN', there is an advantage that the dynamic range DR 'does not become narrow even if dubbing is performed using a recording circuit having an encoder of the multi-stage ADRC.

[Problems to be solved by the invention]

Assuming a digital VTR that compresses image data by ADRC, it is desirable to have a function to prevent dubbing of video software from the viewpoint of copyright protection.

An object of the present invention is to provide a recording / reproducing apparatus and a recording / reproducing method for a digital image signal which have a dubbing prevention function by utilizing the features of different quantization schemes of ADRC.

[Means for solving the problem]

The present invention relates to a first stage of a multi-stage ADRC provided in a recording circuit system.
Encoder (4) and second encoder (5) for non-edge matching quantization, first switching means SW2 for switching between first encoder (4) and second encoder (5), and quantization method Means for adding an ID signal for identifying an ID to a recording signal, means for recording a digital recording signal including the ID signal, means for reproducing a digital reproduction signal, and a reproduction circuit to which the digital reproduction signal is supplied A first decoder (13) for multi-stage ADRC and a second decoder (14) for non-edge matching quantization provided in the system, a means (10) for separating an ID signal from a reproduced signal, and a first decoder ( 13) and second switching means SW4 for switching between the second decoder (14) and the first encoder (4) when recording by the recording circuit system.
Is selected, and at the time of dubbing, the first switching means SW2 is controlled so that the first encoder (4) or the second encoder (5) is selected according to the ID signal in the input data. Second switching means with separated ID signal
This is a digital image signal recording / reproducing device in which SW4 is controlled. Further, the present invention is a method for recording and reproducing a digital image signal as described above.

[Action]

At the time of self-recording / playback, the multistage ADRC encoder 4 is selected by the switching circuit SW2 at the time of recording, and the multistage ADRC is selected at the time of reproduction.
The ADRC decoder 13 is selected. Accordingly, high-quality recording / reproduction can be performed, and image quality deterioration due to dubbing is small. The video software is determined to employ non-edge matching quantization, and an ID signal indicating that fact is inserted. Therefore, as the number of times of dubbing of the video software increases, the deterioration of the image quality increases, and dubbing can be substantially prevented.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. This description is made in the following order.

a. Recording / reproducing circuit b. NEM quantization encoder and decoder c. Multi-stage ADRC encoder d. Modified example a. Recording / reproducing circuit FIG. 1 shows a recording / reproducing circuit according to an embodiment of the present invention as a whole. It is shown. An analog video signal is supplied to an input terminal indicated by reference numeral 1. The A / D converter 2 converts the analog video signal into a digital video signal in which one sample is quantized to 8 bits, for example. This digital video signal is supplied to the input terminal a of the switching circuit SW1.

The input terminal 3 is connected to the other input terminal b of the switching circuit SW1.
Is supplied. The output signal of the switching circuit SW1 is a multi-stage ADRC encoder 4 (in the figure, the multi-stage ADRC is called DS) and NEM quantization ADR.
It is supplied to the C encoder 5. The encoded output of these encoders 4 and 5 is the input terminal c of the switching circuit SW2.
And d respectively.

The output signal of the switching circuit SW2 is supplied to the parity generation circuit 6, where error detection and error correction code encoding are performed. The output of the parity generation circuit 6 is supplied to the addition circuit 7. The addition circuit 7 supplies an ID signal for identifying the quantization method. The switching circuit SW2 is controlled by the ID signal. The output signal of the adding circuit 7 is supplied to the recording circuit 8. The recording circuit 8 performs digital modulation,
Includes recording amplifier, etc. A recording signal from the recording circuit 8 is taken out to an output terminal 9. Although not shown, the output terminal 9
A rotating head is connected, and a recording digital signal is recorded on the magnetic tape as an oblique track. As a recording medium, a disk-shaped medium such as a rewritable optical disk may be used other than the magnetic table.

A digital reproduction signal reproduced from the magnetic tape is supplied from an input terminal 11 to a reproduction circuit 12. The reproduction circuit 12 includes a reproduction amplifier, a digital demodulation circuit, and the like. The output signal of the reproduction circuit 12 is supplied to the input terminal e of the switching circuit SW3. The digital video signal from the input terminal 3 is supplied to another input terminal f of the switching circuit SW3.

The output signal of the switching circuit SW3 is a multi-stage ADRC decoder 13, an NEM quantization ADRC decoder 14, and an ID generation circuit 10.
Supplied to The decoded output of the decoder 13 is supplied to the input terminal g of the switching circuit SW4. The decoded output of the decoder 14 is supplied to the input terminal h of the switching circuit SW4.

The switching circuit SW4 is controlled by an ID signal from the ID generation circuit 10. The decoded signal from the switching circuit SW4 is supplied to the error correction and correction circuit 15. The error correction and correction circuit 15 detects and corrects errors generated in the process of recording and reproduction, and corrects uncorrectable errors by means of average value interpolation or the like. The output signal of the error correction and correction circuit 15 is D /
The signal is supplied to the A converter 16 and the mixing circuit 18. A reproduced analog signal from the D / A converter 16 is taken out to an analog output terminal 17. In the mixing circuit 18, the reproduced digital video signal
A signal is added. A reproduced digital video signal including an ID signal from the mixing circuit 18 is taken out to a digital output terminal 19.

The switching circuits SW1 to SW4 of the recording / reproducing circuit shown in FIG. 1 are controlled by a controller (not shown) according to the operation mode, as shown in FIG. The ID signal is one bit, and “0” (logical 0) of the ID signal indicates multi-stage ADRC quantization, and “1” indicates NEM quantization.

Mode 1 is an operation that performs recording and playback on the same VTR,
This is a so-called self-recording operation. During recording in mode 1, an ID signal of “0” is generated from the ID generation circuit 10. An analog input or a digital input is selected by the switching circuit SW1. (ID = "0"), the switching circuit SW
2 input terminal c is selected. Therefore, the encoded output from the multi-stage ADRC encoder 4 is selected by the switching circuit SW2. A digital recording signal to which the ID signal is added is recorded on a magnetic tape.

At the time of reproduction in mode 1, the reproduction digital signal from the magnetic tape is supplied to the input terminal 11, and the reproduction digital signal is supplied to the decoders 13, 14 and the ID generation circuit 10 via the reproduction circuit 12 and the input terminal e of the switching circuit SW3. Is done. ID
Since the ID signal separated by the generation circuit 10 (ID = "0"), the input terminal g of the switching circuit SW4 is selected.
Therefore, the decoded output of the decoder 13 of the multi-stage ADRC is selected. An analog video signal is obtained at the output terminal 17, and a digital video signal is obtained at the output terminal 19. This digital video signal is used for recording on another VTR during dubbing.

Mode 2 is an operation for reproducing video software created in advance by a specialized company such as a movie company. In the case of video software, it is defined that NEM quantization is used, and an ID signal of "1" is recorded on a magnetic tape together with a digital signal. In the mode 2, since the digital reproduction signal is used, the input terminal e of the switching circuit SW3 is used.
Is selected. Further, since the ID signal of "1" is separated by the ID generation circuit 10, the input terminal h of the switching circuit SW4 is selected. Therefore, the encoded output of the NEM quantization decoder 14 is selected, and a high-quality video software playback image can be viewed.

Mode 3 is a dubbing mode. The tape (not video software) recorded by the VTR is reproduced, and the digital reproduction output is supplied to the input terminal 3. The input terminal b of the switching circuit SW1 is selected, and the switching circuit SW3
Input terminal f is selected. The ID signal of “0” inserted at the time of recording (mode 1) is separated by the ID generation circuit 10.
Therefore, the input terminal c of the switching circuit SW2 is selected, and the input terminal g of the switching circuit SW4 is selected.
Thus, the signal recorded by the multi-stage ADRC is
, Decoding can be performed with good image quality.

In the dubbing mode 3, when the video software is to be dubbed, the switching circuit SW2 is connected to the input terminal d because the ID signal recorded in the video software is “1”.
Select Therefore, the encoder 5 for NEM quantization is selected. The encoded output of the encoder 5 to which the ID signal “1” is added is recorded. Due to the NEM quantization, the width of the dynamic range DR is narrowed, and the reproduced image quality of the dubbed video software is lower than the original image quality.
As the number of dubbing increases, the image quality deteriorates. Therefore, dubbing of video software can be substantially prevented.

b. NEM Quantization Encoder and Decoder FIG. 3 shows an example of the NEM encoder 5, in which video data from an input terminal indicated by 21 is arranged by a blocking circuit 22 from a scanning line order to a data order in a block order. Is converted. A screen of one frame or one field is subdivided into (8 × 8 = 64 pixels) blocks as shown in FIG. The output signal of the blocking circuit 22 is supplied to the maximum value / minimum value detection circuit 23 and the delay circuit 24. Detection circuit 23
Detects the maximum value MAX and the minimum value MIN of the block. The delay circuit 24 detects the maximum value MAX and the minimum value MIN,
Delay data. The calculation of (MAX−MIN) is performed in the subtraction circuit 25, and the dynamic range DR is obtained from the subtraction circuit 25. In the subtraction circuit 26, the minimum value MIN is subtracted from the video data from the delay circuit 24, and the video data PDI from which the minimum value has been removed is obtained from the subtraction circuit 26.

The output data of the subtraction circuit 26 and the dynamic range DR are supplied to the quantization circuit 27. From the quantization circuit 27, a code signal DT having a bit number smaller than the original bit number (8 bits), for example, 4 bits is obtained. The quantization circuit 27 performs quantization adapted to the dynamic range DR. That is, FIG.
In the same manner as in the case of 2 bits, the video data PDI from which the minimum value has been removed is divided by the quantization step Δ obtained by equally dividing the dynamic range DR by (2 ⁴ = 16), and the value obtained by rounding down the quotient is converted to an integer. This is the code signal DT. The quantization circuit 27
It can be composed of a division circuit or ROM.

Dynamic range DR, minimum value MIN and code signal DT
Is supplied to the framing circuit 28, and the transmission data is extracted from the output terminal 29. The framing circuit 28 forms transmission data to which the dynamic range DR, the minimum value MIN, and the code signal DT are arranged byte-serial and to which a synchronization signal is added.

FIG. 5 shows an example of the decoder 14 for NEM quantization. 31
The data from the input terminal indicated by is supplied to the frame decomposition circuit 32. The dynamic range DR and the code signal DT from the frame decomposition circuit 32 are supplied to the decoding circuit 33. The decoding circuit 33 is constituted by a circuit for multiplying the quantization step by the code signal or a ROM in which a table is stored. The output data of the decoding circuit 33 and the minimum value MIN from the frame decomposing circuit 32 are supplied to an adding circuit 34, and the adding circuit 34
To obtain the decoded value. This decoded value is the block decomposition circuit
The data order is supplied to 35 and the data order is converted from the block order to the television scan order. The decoded output of the decoder 14 is obtained at the output terminal 36.

c. Multi-stage ADRC encoder The multi-stage ADRC encoder 4 calculates the maximum value MAX and the minimum value MIN of a plurality of pixel data included in the block, and calculates the original dynamic range DR for each block from the maximum value MAX and the minimum value MIN. A maximum and minimum value detection circuit to be detected,
When the original dynamic range DR is divided into a plurality of level ranges corresponding to a smaller number of bits than the original quantization bit number, the input image data included in the maximum level range and the minimum level range respectively are extracted, and the maximum level is extracted. A circuit for forming a first average value MAX 'of the input image data included in the range and a second average value MIN' of the input image data included in the minimum level range; Average value of M
Calculate the modified dynamic range DR 'from IN'
An encoding circuit for subtracting the average value MIN 'from the input image signal, and encoding the subtracted output in accordance with the modified dynamic range DR' with less than the original number of quantization bits.

FIG. 6 shows an example of the encoder 4 of the multi-stage ADRC. The input digital video signal from the input terminal 41 is converted by the blocking circuit 42 into a continuous signal for each two-dimensional block having a size of (8 lines × 8 pixels = 64 pixels).

The output signal of the blocking circuit 42 is supplied to the maximum value / minimum value detection circuit 43 and the delay circuit 44. The maximum value / minimum value detection circuit 43 detects a minimum value MIN and a maximum value MAX for each block. The subtraction circuit 57 subtracts (MAX−MIN), and the dynamic range DR is detected. The pixel data from the delay circuit 44 is supplied to the comparison circuits 45 and 46.

The maximum value MAX from the maximum value / minimum value detection circuit 43 is supplied to the subtraction circuit 47, and the minimum value MIN is supplied to the addition circuit. The value Δ of one quantization step width when NEM quantization is performed is supplied from the bit shift circuit 49 to the subtraction circuit 47 and the addition circuit 48. The bit shift circuit 49 shifts the dynamic range DR by 4 bits so as to divide (DR / 2 ⁴ ) when the number of bits is 4 bits. The threshold value of (MAX−Δ) is obtained from the subtraction circuit 47, and the threshold value of (MIN + Δ) is obtained from the addition circuit 48. The threshold values from the subtraction circuit 47 and the addition circuit 48 are supplied to comparison circuits 45 and 46, respectively.

The output signal of the comparison circuit 45 is supplied to the AND gate 50, and the output signal of the comparison circuit 46 is supplied to the AND gate 51. Input data from the delay circuit 44 is supplied to the AND gates 50 and 51. The output signal of the comparison circuit 45 becomes high level when the input data is larger than the threshold value. Therefore, the output terminal of the AND gate 50 has the pixel of the input data included in the maximum level range of (MAX to MAX-Δ). The data is extracted. The output signal of the comparison circuit 46 becomes high level when the input data is smaller than the threshold value. Therefore, the output terminal of the AND gate 51 receives the pixel data of the input data included in the minimum level range of (MIN to MIN + Δ). Is extracted.

The output signal of the AND gate 50 is supplied to the averaging circuit 52, and A
The output signal of the ND gate 51 is supplied to the averaging circuit 53. These averaging circuits 52 and 53 calculate an average value for each block, and a reset signal of a block cycle is supplied from the terminal 54 to the averaging circuits 52 and 53. Averaging circuit 52
Obtains an average value MAX 'of pixel data belonging to the maximum level range of (MAX-MAX-.DELTA.). The averaging circuit 53 outputs an average value of pixel data belonging to the minimum level range of (MIN-MIN + .DELTA.). MIN 'is obtained. Average value from average value MAX '
MIN 'is subtracted by the subtraction circuit 55, and the modified dynamic range DR' is obtained from the subtraction circuit 55.

Further, the average value MIN 'is supplied to the subtraction circuit 56, and the average value MIN' is subtracted from the input data passed through the delay circuit 44.
The data PDI is subtracted in 6 to form the data PDI after the removal of the minimum value. The data PDI and the modified dynamic range DR 'are supplied to the quantization circuit 58. In the quantization circuit 58, as in the case of 2-bit in FIG.
Quantization is performed.

Although not shown, the decoder 13 of the multi-stage ADRC has the same configuration as the decoder 14 in FIG. Multi-stage ADRC decoder
At 13, decoding is performed using the modified dynamic range DR ', code signal DT and minimum value MIN.

d. Modifications In the encoders 4 and 5 described above, buffering for controlling the amount of data generated during a predetermined period, for example, one frame period, to a predetermined value may be performed. The encoders 4 and 5 may share a blocking circuit and a framing circuit, and the decoders 13 and 14 may share a frame decomposition circuit and a block decomposition circuit.

〔The invention's effect〕

According to the present invention, high-quality recording and
Playback and high-quality dubbing are possible, and when playing video software, you can see high-quality playback images. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention, FIG. 2 is a schematic diagram used for explaining control of a switching circuit, and FIG. 3 is a block diagram of an example of an encoder for NEM quantization. FIG. 4 is a schematic diagram used for describing blocks, FIG. 5 is a block diagram of an example of a decoder for NEM quantization, FIG.
FIG. 7 is a block diagram of an example of a multi-stage ADRC encoder, and FIG. 7 is a schematic diagram used for explaining a method of quantizing ADRC. Explanation of main symbols in the drawings SW1 to SW4: Switching circuit, 4: Multistage ADRC encoder, 5: NEM quantization encoder, 7: ID signal addition circuit, 13: Multistage ADRC decoder, 14: NEM quantization decoder.

Claims (2)

(57) [Claims] 1. A multi-stage ADRC first encoder and a non-edge matching quantization second encoder provided in a recording circuit system, and first switching means for switching between the first encoder and the second encoder. Means for adding an ID signal for identifying a quantization method to a recording signal; means for recording a digital recording signal including the ID signal; means for reproducing a digital reproduction signal; A first decoder of multi-stage ADRC and a second decoder of non-edge matching quantization provided in the supplied reproduction circuit system, a unit for separating the ID signal from a reproduction signal, the first decoder and the second decoder And second switching means for switching between two decoders. When recording is performed by the recording circuit system, the first encoder is selected, and when recording is performed, The first switching means is controlled so that the first or second encoder is selected in accordance with an ID signal in input data, and the second ID is used for reproduction in response to the separated ID signal. A digital image signal recording / reproducing apparatus, wherein switching means is controlled. 2. An ID for identifying a quantization method by switching between a first encoder of multi-stage ADRC and a second encoder of non-edge matching quantization provided in a recording circuit system by a first switching means. A signal is added to a recording signal, a digital recording signal including the ID signal is recorded, a digital reproduction signal is reproduced, the ID signal is separated from the reproduction signal, and the signal is provided in a reproduction circuit system to which the digital reproduction signal is supplied. The first decoder of the multi-stage ADRC and the second decoder of the non-edge matching quantization are switched by the second switching means. When recording is performed by the recording circuit system, the first encoder is selected, and when dubbing is performed, Controlling the first switching means so as to select the first or second encoder according to an ID signal in the input data, Recording and reproducing method of a digital image signal and controlling said second switching means in said separated ID signal.