JPH0461580A - Recording and reproducing device for digital picture signal - Google Patents

Abstract

PURPOSE:To prevent dubbing of a video software by selecting multi-stage ADRC and non-edge matching quantization in response to an ID signal in an input data at dubbing, applying non-edge matching quantization and inserting an ID signal representing the quantization in the case of the video software. CONSTITUTION:A coded output from a multi-stage ADRC encoder 4 is selected by a switching circuit SW2 at self-recording. A demodulation output of a multi- stage ADRC encoder 13 is selected at reproduction. In the case of dubbing a video software, an ID signal recorded on the video software is logical 1, then the switching circuit SW2 is thrown to the position of an input terminal (d). Thus, an NEM quantization encoder 5 is selected and a coded output added with an ID signal of logical 1 is recorded. Since the picture quality of the reproduced picture of the video software in dubbing is deteriorated by the NEM quantization, the dubbing of the video software is substantially prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is effective for recording and reproducing devices for digital image signals, particularly for preventing dubbing of video software.

[Summary of the invention]

In this invention, when self-recording and playback, multi-stage ADRC is used to enable high-quality recording and playback, and when dubbing, multi-stage ADRC and non-edge matching I-coupling are performed in response to an ID signal in input data. In the case of video software, dubbing of the video software can be substantially prevented by performing non-edge matching quantization and inserting an ID signal indicating this.

[Conventional technology]

As an encoding method for compressing the amount of transmitted data of a video signal, the applicant of the present application has proposed encoding adapted to dynamic range (referred to as ADRC).

FIG. 7A is used to explain ADRC quantization. Dynamic range DR (maximum value MAX and minimum value 41
A difference of 1EMIN) is calculated for each two-dimensional block consisting of (8 lines x 8 pixels = 64 pixels), for example. Also, from the input pixel data, the minimum level (
minimum value) MIN is removed. The pixel data after the minimum value has been removed is converted into a code signal. In this quantization, the detected dynamic range DR is equally divided into four level ranges A O - A 3 corresponding to a bit number smaller than the original quantization bit number, for example, 2 bits, and each pixel data in the block is This is a process of detecting the level range to which it belongs and generating a code signal indicating this level range.

In Figure 7A, the dynamic range DR of the block is 4.
It is divided into level ranges AO to A3. Pixel data included in the minimum level range AO is encoded as (00), pixel data included in level range A1 is encoded as (01), and pixel data included in level range A2 is encoded as (00).
pixel data included in the maximum level range A3 is encoded as (11). Therefore, 8-bit data of each pixel is compressed into 2-bit data and transmitted.

On the receiving side, the received code signal is at the representative level LO~
Restored to L3. These representative levels LO-L3 are the respective center levels of the level range AO-A3. The quantization shown in FIG. 7A is performed using non-edge matching (NE
(abbreviated as M) is called quantization.

On the other hand, as shown in FIG. 7B, l/
6DR level range AO and 1/6 including maximum value MAX
ADRC quantization in which a DR level range A3 and two 1/3 DR level ranges AI and A2 are set is called edge matching (abbreviated as EM) quantization.

NEM quantization has the advantage of statistically reducing quantization distortion. However, when applied to a digital VTR,
Each time dubbing is performed, the dynamic range DR decreases, resulting in a large degree of deterioration in image quality. EMii childization is
Since the minimum values M, I N and the maximum value MAX are preserved even if dubbing is performed, there is an advantage that the degree of image quality deterioration due to dubbing is small. However, since the widths of the level ranges AI and A2 are larger than in NEM quantization, there is a drawback that quantization distortion is large.

Furthermore, NEM quantization has a problem in that block distortion occurs due to ringing and impulsive noise. In order to solve this problem, the applicant filed the patent application
As described in the specification of No. 2118, a method is proposed in which preprocessing is performed on input data converted into a block structure.

This method is called multi-stage ADRC, and the average value MAX of the input data values included in the maximum level range (7th [A3 in IKA) when the dynamic range is equally divided by the number of ADRC quantization bits. ' and the average value MIN' of the input data included in the minimum level range (AO in Figure 7A) are detected, and as shown in Figure 7C, these average values MAX' and average value MIN' are detected. EM quantization is performed so that these are set to restoration levels L3 and LO, respectively.

In multi-stage ADRC that performs EM quantization after preprocessing with NEM quantization described above, even in blocks that include ringing, the maximum value is not the peak of ringing, but the average value MAχ
', and similarly the minimum value is changed to MIN'.

Since EM quantization is performed within the modified dynamic range DR' determined by MAX' and MIN'', the difference between the restoration level and the restoration level of adjacent blocks is reduced,
Block distortion is prevented from occurring.

In addition, multi-stage ADRC has restoration levels of MAX' and MI.
N', there is an advantage that the dynamic range DR' does not become narrower even when dubbing is performed using a recording circuit having a multi-stage ADRC encoder.

(Problem to be solved by the invention) Digital VTR that compresses image data by ADRC
In this case, it is desirable to have a function to prevent dubbing of video software from the viewpoint of copyright protection.

An object of the present invention is to provide a digital image signal recording/reproducing device that has a dubbing prevention function by utilizing the characteristics of different quantization methods of ADRC.

[Means to solve the problem]

The present invention includes a multi-stage ADRC first encoder (4), a non-edge matching quantization second encoder (5), and a first encoder (4) provided in a recording circuit system.
and a first switching means sw2 for switching the second encoder (5); a means (]O) for adding an ID signal to the recording signal for identifying the quantization method; A means for recording, a means for reproducing a digital reproduction signal, and a multi-stage ADRC provided in a reproduction circuit system to which the digital reproduction signal is supplied.
a first decoder (13) and a second non-edge matching quantization decoder (14); means (10) for separating the ID signal from the reproduced signal; It consists of a second switching means SW4 for switching the decoder (14), and when recording in the recording circuit system, the first encoder (4) is selected, and when dubbing, the first encoder (4) is selected according to the ID signal in the input data. Encoder (4) or second encoder (
The first switching means SW2 is controlled so that 5) is selected, and during reproduction, the second switching means SW4 is controlled by the separated ID signal.

[Effect]

During self-recording/playback, the multi-stage ADRC encoder 4 is selected by the switching circuit SW2 during recording, and the multi-stage ADRC decoder 13 is selected during playback. Therefore, it is possible to record and reproduce high quality images, and there is little deterioration in image quality due to dubbing. Video software is required to use non-edge matching quantization, and an ID signal indicating this is inserted. Therefore, as the number of dubbing of video software increases, the deterioration of image quality increases, and dubbing can be practically prevented.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. This description is given in the following order.

a. Recording/reproducing circuit, NEM quantization encoder and decoder C9 multi-stage A
DRC encoder d, modification a, recording/reproducing circuit FIG. 1 shows the entire recording/reproducing circuit of an embodiment of the present invention. An analog video signal is supplied to an input terminal indicated by 1. The A/D converter 2 converts the analog video signal into a digital video signal in which one sample is quantized to 8 bits, for example. This digital video signal is supplied to the input terminal a of the switching circuit SWI.

Input terminal 3 to other input terminals of switching circuit SWI
A digital video signal is supplied from the The output signal of the switching circuit SWI is sent to the multi-stage ADRC encoder 4.
(In the figure, multi-stage ADRC is called DS) and N
The signal is supplied to an ADRC encoder 5 for EM quantization. The encoded outputs of encoders 4 and 5 are supplied to input terminals C and d of switching circuit SW2, respectively.

The output signal of the switch noting circuit SW2 is supplied to the parity generation circuit 6, where error detection and error correction code encoding are performed. The output of the parity generation circuit 6 is the adder circuit 7
supplied to The adder circuit 7 is supplied with an ID signal for identifying the quantization method. The switching circuit SW2 is controlled by this ID signal. The output signal of the adder circuit 7 is supplied to the recording circuit 8. The recording circuit 8 includes digital modulation, a recording amplifier, and the like. A recording signal from the recording circuit 8 is taken out to an output terminal 9. Although not shown, a rotary head is connected to the output terminal 9, and recording digital signals are recorded as diagonal tracks on the magnetic tape. As the recording medium, in addition to the magnetic table, a disk-shaped medium such as a rewritable optical disk may be used.

A digital reproduction signal reproduced from the magnetic tape is supplied from an input terminal 11 to a reproduction circuit 12.

The reproduction circuit 12 includes a reproduction amplifier, a digital demodulation circuit, and the like. The output signal of the reproduction circuit 12 is transmitted to the switching circuit SW.
It is supplied to the input terminal e of No. 3. Switching circuit SW3
The digital video signal from the input terminal 3 is supplied to the other input terminal f of.

The output signal of the switching circuit SW3 is supplied to the multi-stage ADRC decoder 13, the NEM quantization ADRC decoder 14, and the ID generation circuit 10.

The decoded output of the decoder 13 is supplied to the input terminal g of the switching circuit SW4. The decoded output of the decoder 14 is supplied to the input terminal of the switching circuit SW4.

The switching circuit SW4 receives the I from the ID generation circuit 10.
Controlled by D signal. The decoded signal from switching circuit SW4 is supplied to error correction and modification circuit 15. The error correction and modification circuit 15 detects and corrects errors that occur during the recording/reproduction process, and corrects uncorrectable errors by means of average value interpolation or the like. Error correction and modification circuit 15
The output signal of is supplied to the D/A converter 16 and the mixing circuit 18. A reproduced analog signal from the D/A converter 6 is taken out to an analog output terminal 17. In the mixing circuit 18, an ID signal is added to the reproduced digital video signal.

A reproduced digital video signal including the ID signal from the mixing circuit 18 is taken out to a digital output terminal 19.

The switching circuits SW1 to SW4 of the recording/reproducing circuit shown in FIG. 1 described above are controlled by a controller (not shown) as shown in FIG. 2 depending on the mode of operation. ID
The signal has 1 pitch, “0” (logical 0) of the ID signal indicates quantization of multi-stage ADRC, and “1” indicates quantization of N
EM quantization is shown.

Mode l is an operation in which recording and playback are performed on the same VTR;
This is a so-called self-recording/playback operation. During recording in mode 1, an ID signal of "0" is generated from the ID generation circuit 1o. Analog input or digital input is selected by switching circuit SW1.

(TD-“0′), the input terminal C of the switching circuit sw2 is selected. Therefore, the encoded output from the multi-stage ADRC encoder 4 is selected by the switching circuit SW2. Digital recording signals are recorded on magnetic tape.

During playback in mode J, a playback digital signal from the magnetic tape is supplied to the input terminal 11, and is sent to the decoder 13 via the playback circuit 12 and the input terminal e of the switching circuit SW3.
．． 14 and the ID generation circuit 10 are supplied with reproduced digital signals. The ID signal separated by the ID4 forming circuit 10 is (
ID-“0”), the input terminal g of the switching circuit SW4 is selected. Therefore, the decoded output of the multi-stage ADRC decoder 13 is selected. An analog video signal is obtained at the output terminal 17, and a digital video signal is obtained at the output terminal 19. This digital video signal is used for recording on another VTR during dubbing.

Mode 2 is an operation in which video software created in advance by a specialized company such as a movie company is played back. In the case of video software, it is specified that NEM cover is used, and a 1" ID signal is recorded on the magnetic tape together with a digital signal. In this mode 2, a digital playback signal is used, so The input terminal e of the switching circuit SW3 is selected. Also, since the ID signal of "1" is separated by the ID generation circuit 10, the input terminal e of the switching circuit SW4 is selected.Therefore, the NEM quantization decoder 14 encoded outputs are selected, and the reproduced image of the high-quality video software can be viewed.

Mode 3 is a dubbing mode. A tape (not video software) recorded on a VTR is played back, and its digital playback output is supplied to the input terminal 3. The input terminal f of the switching circuit SWI is selected, and the input terminal f of the switching circuit SW3 is selected. When recording (mode 1)
The “O′” ID signal inserted in the ID generation circuit 1
Separated by 0. Therefore, input terminal C of switching circuit SW2 is selected, and input terminal g of switching circuit SW4 is selected. In this way, since the signal recorded by multi-stage ADRC is decoded by the multi-stage ADRC decoder 13, dubbing with good image quality can be performed.

In dubbing mode 3, when attempting to dub video software, the ID signal recorded in the video software is "BI", so the switching circuit SW 2 selects the input terminal d. Therefore, the NEM quantization encoder 5 is selected. The encoded output of encoder 5 to which the ID signal of "1" is added will be recorded. 20NE
M quantization narrows the width of the dynamic range DR, and the quality of the reproduced image of the dubbed video software deteriorates compared to the original. As the number of dubbing increases, the image quality deteriorates. Therefore, dubbing of video software can be virtually prevented.

b. NEM quantization encoder and decoder Figure 3 is:
An example of the NEM encoder 5 is shown, in which video data from an input terminal indicated by 21 is sent to a blocking circuit 22, where the data arrangement is converted from the scanning line order to the program order. As shown in FIG. 4, one frame or one field screen is subdivided into blocks of (8×8=64 pixels).

The output signal of the blocking circuit 22 is supplied to a maximum value and minimum value detection circuit 23 and a delay circuit 24.

The detection circuit 23 detects the maximum value MAX and minimum value MI of the block.
Detect N. The delay circuit 24 delays the data for the time it takes to detect the maximum value MAX and minimum value MIN. The subtraction circuit 25 calculates (MAX-MIN), and the subtraction circuit 25 obtains the dynamic range DR. In the subtraction circuit 26, the minimum value MIN is subtracted from the video data from the delay circuit 24, and video data PDI from which the minimum value has been removed is obtained from the subtraction circuit 26.

Output data of subtraction circuit 26 and dynamic range DR
is supplied to the quantization circuit 27. A code signal DT having a smaller number of bits than the original number of bits (8 bits), for example 4 bits, is obtained from the quantization circuit 27. The quantization circuit 27 is
Quantization adapted to the dynamic range DR is performed. In other words, as in the case of 2-focus shown in FIG.
The video data PDI from which the minimum value has been removed is divided, and the value obtained by rounding down the quotient to an integer is set as the code signal DT. The quantization circuit 27 can be composed of a division circuit or a ROM.

The minimum value MIN of the dynamic range DR1 and the code signal DT are supplied to the framing circuit 28, and the transmission data is taken out to the output terminal 29.

The framing circuit 28 forms transmission data in which the minimum value MIN of the dynamic range DR3 and the code signal DT are arranged in a hide serial manner and a synchronization signal is added.

FIG. 5 shows an example of the decoder 14 for NEM quantization.

Data from the input terminal indicated by 31 is sent to the frame decomposition circuit 3.
2. Dynamic range DR and code signal DT from frame decomposition circuit 32 are supplied to decoding circuit 33 . The decoding circuit 33 is a circuit for multiplying the quantization step and the code signal, or an R circuit in which a table is stored.
It is composed of OM. The output data of the decoding circuit 33 and the minimum value MIN from the frame decomposition circuit 32 are supplied to the addition circuit 34, and a decoded value is obtained from the addition circuit 34.

This decoded value is supplied to a blocking circuit 35, which converts the data order from the block order to the television scanning order. The decoded output of the decoder 14 is obtained at the output terminal 36.

C1 Multi-stage A, D RC encoder Multi-stage ADRC encoder 4 calculates the maximum value MAX and minimum value MIN of a plurality of pixel data included in a block, and calculates the original dynamic range for each block from the maximum value MAX and minimum value MIN. A maximum value and minimum value detection circuit for detecting DR, and a maximum level range and a minimum level range when the original dynamic range DR is divided into a plurality of level ranges corresponding to a number of bits smaller than the original quantization bit number. The input image data included in each are extracted, and the first average (iM
a circuit for forming a second average value MIN' of input image data included in Aχ' and the minimum level range; and a dynamic range DR' corrected from the first average value MAX' and the second average value MIN'. It consists of an encoding circuit that calculates the average value MIN' from the input image signal, and encodes the subtracted output with less than the original quantization bit number and according to the corrected dynamic range DR'. be.

FIG. 6 shows an example of the multi-stage ADRC encoder 4.

The input digital video signal from the input terminal 41 is processed by the blocking circuit 42 (8 lines x 8 pixels = 64 pixels).
Each two-dimensional block of size is converted into a continuous signal.

The output signal of the blocking circuit 42 is supplied to a maximum value/minimum value detection circuit 43 and a delay circuit 44 .

The maximum value/minimum value detection circuit 43 detects the minimum value M for each block.
IN, detect the maximum value MAX. In the subtraction circuit 57, (M
AX-MIN) is subtracted, and the dynamic range DR
is detected. Pixel data from the delay circuit 44 is supplied to a comparison circuit 45 and a comparison circuit 46.

The maximum value MAX from the maximum value/minimum value detection circuit 43 is supplied to a subtraction circuit 47, and the minimum value MIN is supplied to an addition circuit 48. The subtraction circuit 47 and the addition circuit 48 are supplied with a value Δ of one quantization step width when NEM quantization is performed by the focus shift circuit 49. The bit software circuit 49 calculates (DR/2') when the number of focuses is 4 bits.
), the dynamic range DR is divided by 4.
It is configured to shift bits. A threshold value of (MAX-Δ) is obtained from the subtraction circuit 47, and the threshold value of (MAX-Δ) is obtained from the addition circuit 48.
gives the threshold value (to M I N ). Threshold values from these subtraction circuit 47 and addition circuit 48 are supplied to comparison circuits 45 and 46, respectively.

The output signal of comparison circuit 45 is supplied to AND gate 50, and the output signal of comparison circuit 46 is supplied to AND gate 51. AND gates 50 and 51 are supplied with input data from delay circuit 44 . The output signal of the comparison circuit 45 becomes high level when the input data is larger than the threshold value, and therefore, the output terminal of the AND gate 50 has (M
Pixel data of input data included in the maximum level range of AX-MAX-Δ) is extracted. The output signal of the comparator circuit 46 becomes high level when the input data is smaller than the threshold value, and therefore, the output terminal of the AND gate 51 has (
Pixel data of the input data included in the minimum level range of MIN-MIN+Δ) is extracted.

The output signal of AND gate 50 is supplied to averaging circuit 52, and the output signal of AND gate 51 is supplied to averaging circuit 53. These averaging circuits 52 and 53 calculate an average value for each block, and a block period reset signal is supplied from a terminal 54 to the averaging circuits 52 and 53. From the averaging circuit 52, (MAX~MAX-
Average value MA of pixel data belonging to the maximum level range of Δ)
χ' is obtained, and from the averaging circuit 53, (MIN~MI
An average value MIN' of the pixel data belonging to the minimum level range of N+Δ) is obtained. Average value MAX' to average value MIN
- is subtracted by the subtraction circuit 55, and the corrected dynamic range DR' is obtained from the subtraction circuit 55.

Further, the average value MrN' is supplied to the subtraction circuit 56, and the average value MIN' is subtracted from the input data via the delay circuit 44 in the subtraction circuit 56, and the data P after the minimum value is removed.
A DI is formed. This data PDI and the modified dynamic range DR' are supplied to a quantization circuit 58. The quantization circuit 58 performs 4-bit OEM quantization, similar to the 2-bit case in FIG. 7C.

Although not shown, the multi-stage ADRC decoder 13 has the same configuration as the decoder 14 in FIG. 5.

The multi-stage ADRC decoder 13 performs decoding using the corrected dynamic range DR', code signal DT, and minimum value MIN.

d. Modification In the encoders 4 and 5 described above, the predetermined period, for example, 1
Buffering may be performed to control the amount of data generated during a frame period to a predetermined value.

Further, the blocking circuit and the framing circuit may be shared between the encoders 4 and 5, and the decoders 13 and 14
The frame decomposition circuit and the frame decomposition circuit may be shared between the two.

〔Effect of the invention〕

According to this invention, high-quality recording and playback and high-quality dubbing are possible during self-recording and playback, and high-quality playback images can be viewed when playing back video software. When dubbing software, image quality deteriorates significantly, and dubbing can be practically prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a route diagram used to explain the control of the switching circuit, and FIG. 3 is a block diagram of an example of an encoder for NEM quantization. Figure 4 is a route map used to explain the blocks.
FIG. 5 is a block diagram of an example of a decoder for NEM quantization,
FIG. 6 is a block diagram of an example of a multi-stage ADRC encoder, and FIG. 7 is a route diagram used to explain the ADRC quantization method. Explanation of main symbols in the drawings SWI to SW4 Niswitching circuit, 4: Multi-stage ADR
C encoder, 5: NEM quantization encoder, 1:10 signal addition circuit, 13: Multi-stage ADRC (D decoder, 14: NEM quantization decoder. Agent: Patent attorney Masato Sugiura EMf condensation quantization No. Figure 7 Another part of the switching circuit Figure 2

Claims (1)

[Claims] A first encoder of a multi-stage ADRC provided in a recording circuit system and a second encoder of non-edge matching quantization, and a first switching between the first encoder and the second encoder. means for adding an ID signal for identifying a quantization method to a recording signal; means for recording a digital recording signal including the ID signal; means for reproducing a digital reproduction signal; and means for reproducing a digital reproduction signal. a first decoder of a multi-stage ADRC and a second decoder of non-edge matching quantization provided in a reproduction circuit system to which the ID signal is supplied; means for separating the ID signal from the reproduction signal;
decoder and a second switching means for switching the second decoder, when recording in the recording circuit system, the first encoder is selected, and when dubbing, the first encoder is selected according to the ID signal in the input data. The first switching means is controlled so that the first encoder or the second encoder is selected, and during playback, the second switching means is controlled by the separated ID signal. Image signal recording/playback device.